LFX125EB-05FH516C Lattice, LFX125EB-05FH516C Datasheet - Page 2

• Manufacturer Part Number: LFX125EB-05FH516C
• Description: FPGA - Field Programmable Gate Array Use LFX125EB-05F516C
• Manufacturer: Lattice

Specifications of LFX125EB-05FH516C

• Number Of Gates: 139 K
• Number Of Logic Blocks: 1936
• Number Of I/os: 22
• Operating Supply Voltage: 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-516
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 135

Lattice Semiconductor
ispXPGA Family Overview
The ispXPGA family of devices provides the ideal vehicle for the creation of high-performance logic designs that
are both non-volatile and infinitely re-programmable. Other FPGA solutions force a compromise, being either re-
programmable or non-volatile. This family couples this capability with a mainstream architecture containing the fea-
tures required for today’s system-level design.
The ispXPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial
communications while the lower-cost “E-Series” supports the same high-performance FPGA fabric without the
sysHSI Block.
Electrically Erasable CMOS (E
These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applica-
tions. This capability also means that expensive external configuration memories are not required and that designs
can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if
desired. Both the SRAM and E
dard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIG™ peripheral port.
The family spans the density and I/O range required for the majority of today’s logic designs, 139K to 1.25M system
gates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies, provid-
ing easy integration into the overall system.
System-level design needs are met through the incorporation of sysMEM dual-port memory blocks, sysIO
advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications are sup-
ported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serialization
(SERDES).
The ispLEVER™ design tool from Lattice allows easy implementation of designs using the ispXPGA product. Syn-
thesis library support is available for major logic synthesis tools. The ispLEVER tool takes the output from these
common synthesis packages and place and routes the design in the ispXPGA product. The tool supports floor
planning and the management of other constraints within the device. The tool also provides outputs to common
timing analysis tools for timing analysis.
To increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for the
ispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while using
pre-designed blocks to implement standard functions such as bus interfaces, standard communication interfaces,
and memory controllers.
Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide design-
ers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz.
Certain designs can run at over 300MHz. Table 2 details the performance of several building blocks commonly
used by logic designers.
Table 2. ispXPGA Speed Performance for Typical Building Blocks
8:1 Asynch MUX
1:32 Asynch Demultiplexer
8 x 8 2-LL Pipelined Multiplier
32-bit Up/Down Counter
32-bit Shift Register
2
CMOS cells can be programmed and verified through the IEEE 1532 industry stan-
2
CMOS) memory cells provide the ispXPGA family with non-volatile capability.
Function
2
Performance
150 MHz
125 MHz
225 MHz
290 MHz
360 MHz
ispXPGA Family Data Sheet