OR2C08A3M84I-D Lattice, OR2C08A3M84I-D Datasheet - Page 4

• Manufacturer Part Number: OR2C08A3M84I-D
• Description: FPGA - Field Programmable Gate Array Use ECP/EC or XP LatticeXP
• Manufacturer: Lattice

Specifications of OR2C08A3M84I-D

• Product Category: FPGA - Field Programmable Gate Array
• Number Of Gates: 21.6 K
• Number Of I/os: 224
• Maximum Operating Frequency: 40 MHz
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: OR2C-84
• Minimum Operating Temperature: - 40 C

ORCA Series 2 FPGAs
Description
The ORCA Foundry Development System is used to process a design from a netlist to a configured FPGA. This
system is used to map your design onto the ORCA architecture and then place and route it using ORCA Foundry’s
timing-driven tools. The development system also includes interfaces and libraries to popular CAE tools for design
entry, synthesis, and simulation. Some examples of the resources required and the performance that can be
achieved using these devices are represented in Table 2.
The FPGA’s functionalitiy is determined by internal configuration RAM. The FPGA’s internal initialization/configura-
tion circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of
several configuration modes. The configuration data resides externally in an EEPROM, EPROM, or ROM on the
circuit board, or any other storage media. Serial ROMs provide a simple, low pin count method for configuring
FPGAs, while the peripheral and JTAG configuration modes allow for easy, in-system programming (ISP).
Table 2 . ORCA Series 2 System Performance
1. Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers).
4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address
5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address mul-
6. Implemented using 16 x 2 synchronous dual-port RAM mode.
7. OR2TxxB available in -7 and -8 speeds only.
4
16-bit Loadable Up/Down Counter
16-bit Accumulator
8 x 8 Parallel Multiplier:
32 x 16 RAM (synchronous):
36-bit Parity Check (internal)
32-bit Address Decode (internal)
Multiplier Mode, Unpipelined
ROM Mode, Unpipelined
Multiplier Mode, Pipelined
Single Port (read and write/
cycle)
Single Port
Dual Port
multiplexer.
tiplexer.
4
6
5
Function
(continued)
2
3
1
PFUs
3.25
22
44
16
#
4
4
9
9
9
4
51.0
51.0
14.2
41.5
50.5
21.8
38.2
38.2
13.9
12.3
-2A
66.7
66.7
19.3
55.6
69.0
28.6
52.6
52.6
11.0
-3A
9.5
87.0
87.0
25.1
71.9
82.0
36.2
69.0
83.3
-4A
9.1
7.5
104.2
104.2
103.1
31.0
87.7
45.5
86.2
90.9
-5A
7.4
6.1
Speed Grade
129.9
129.9
107.5
125.0
36.0
53.8
92.6
92.6
-6A
5.6
4.6
144.9
144.9
122.0
142.9
40.3
62.5
96.2
96.2
-7A
5.2
4.3
Lattice Semiconductor
December 2005
131.6
131.6
103.1
123.5
37.7
57.5
97.7
97.7
-7B
6.1
4.8
Product Brief
149.3
149.3
120.5
142.9
112.4
112.4
44.8
69.4
-8B
5.1
4.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ns
ns