1894K-43LF IDT, 1894K-43LF Datasheet - Page 15

• Manufacturer Part Number: 1894K-43LF
• Description: Ethernet ICs 3.3V 10/100 PHY RMII
• Manufacturer: IDT

Specifications of 1894K-43LF

• Rohs: yes
• Part # Aliases: ICS1894K-43LF

Pins for Monitoring the Data Link table
Note:
1. During either power-on reset or hardware reset, each
multi-function configuration pin is an input that is sampled
when the ICS1894-32 exits the reset state. After sampling is
complete, these pins are output pins that can drive status
LEDs.
2. A software reset does not affect the state of a
multi-function configuration pin. During a software reset, all
multi-function configuration pins are outputs.
3. Each multi-function configuration pin must be pulled
either up or down with a resistor to establish the address of
the ICS1894-32. LEDs may be placed in series with these
The following figure shows typical biasing and LED connections for the ICS1894-32.
The above circuit decodes the PHY address = 1
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
P0/LED0
P1/ISO/LED1
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Pin
Link, Activity, Tx, Rx, COL, Mode, Dplx
Link, Activity, Tx, Rx, COL, Mode, Dplx
Status Events that drive the LEDs
LED1
P1/ISO/LED1
32
ICS1894-32
10KΩ
1KΩ
P0/LED0
31
LED0
VDD
resistors to provide a designated status indicator as
described in the Pins for Monitoring the Data Link table. Use
1KΩ resistors.
Caution: Pins listed in the Pins for Monitoring the Data Link
table must not float.
4. As outputs, the asserted state of a multi-function
configuration pin is the inverse of the sense sampled during
reset. This inversion provides a signal that can illuminate an
LED during an asserted state. For example, if a
multi-function configuration pin is pulled down to ground
through an LED and a current-limiting resistor, then the
sampled sense of the input is low. To illuminate this LED for
the asserted state, the output is driven high.
5. Adding 10KΩ resistors across the LEDs ensures the PHY
address is fully defined during slow VDD power-ramp
conditions.
6. PHY address 00 tri-states the MII interface. (Do not select
PHY address 00 unless you want the MII tri-stated.)
10KΩ
1KΩ
15
ICS1894-32
PHYCEIVER
REV M 021512