1894KI-40LF IDT, 1894KI-40LF Datasheet - Page 9

• Manufacturer Part Number: 1894KI-40LF
• Description: Ethernet ICs 3.3V 10/100 PHY RMII
• Manufacturer: IDT

Specifications of 1894KI-40LF

• Rohs: yes
• Part # Aliases: ICS1894KI-40LF

Receive Error (RXER)
RXER is asserted for one or more RXCLK periods to
indicate that an error (e.g. a coding error or any error that a
PHY is capable of detecting, and that may otherwise be
undetectable by the MAC sub-layer) was detected
somewhere in the frame presently being transferred from
the PHY. RXER transitions synchronously with respect to
RXC. While RXDV is de-asserted, RXER has no effect on
the MAC.
Carrier Sense (CRS)
CRS is asserted and de-asserted as follows:
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•
Collision (COL)
COL is asserted in half-duplex mode whenever the
transmitter and receiver are simultaneously active on the
line. This is used to inform the MAC that a collision has
occurred during its transmission to the PHY.
COL transitions asynchronously with respect to TXCLK and
RXCLK.
Reduced MII (RMII) Data Interface
The Reduced Media Independent Interface (RMII) specifies
a low pin count Media Independent Interface (MII). It
provides a common interface between physical layer and
MAC layer devices, and has the following key
characteristics:
•
•
•
•
In RMII mode, a 50 MHz reference clock is connected to
REFIN(pin 30).
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
In 10Mbps mode, CRS assertion is based on the
reception of valid preambles. CRS de-assertion is based
on the reception of an end-of-frame (EOF) marker.
In 100Mbps mode, CRS is asserted when a
start-of-stream delimiter, or /J/K symbol pair is detected.
CRS is deasserted when an end-of-stream delimiter, or
/T/R symbol pair is detected. Additionally, the PMA layer
de-asserts CRS if IDLE symbols are received without
/T/R.
Supports 10Mbps and 100Mbps data rates.
Uses a single 50MHz reference clock provided by the
MAC or the system board.
Provides independent 2-bit wide (di-bit) transmit and
receive data paths.
Contains two distinct groups of signals: one for
transmission and the other for reception.
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ICS1894-40
PHYCEIVER
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