1894KI-32LFT IDT, 1894KI-32LFT Datasheet - Page 41
1894KI-32LFT
Manufacturer Part Number
1894KI-32LFT
Description
Ethernet ICs 3.3V 10/100 PHY RMII
Manufacturer
IDT
Datasheet
1.1894KI-32LF.pdf
(50 pages)
Specifications of 1894KI-32LFT
Rohs
yes
Part # Aliases
ICS1894KI-32LFT
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10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
The 10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) shows the timing diagram for
the time periods.
10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
TXEN
TXCLK
CRS
The table below lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex
transmission. The time periods consist of timings of signals on the following pins:
•
•
•
Period
Time
TXEN
TXCLK
CRS
t1
t2
TXEN Asserted to CRS Assert
TXEN De-Asserted to CRS De-Asserted
t1
Parameter
t2
Conditions
41
Min.
0
0
Typ.
–
2
ICS1894-32
Max.
2
4
Bit times
Bit times
PHYCEIVER
Units
REV M 021512
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