GLS55VD020-60-C-TQWE-DZ019 Greenliant, GLS55VD020-60-C-TQWE-DZ019 Datasheet - Page 16

• Manufacturer Part Number: GLS55VD020-60-C-TQWE-DZ019
• Description: Flash ATA Media 60MHz 2.7V Commercial
• Manufacturer: Greenliant

Specifications of GLS55VD020-60-C-TQWE-DZ019

• Rohs: yes
• Memory Type: NAND Flash
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100

Data Sheet
SOFTWARE INTERFACE
NAND Controller Drive Register Set Definitions and Protocol
This section defines the drive registers for the NAND Controller and the protocol used to address them.
NAND Controller Addressing
The I/O decoding for an NAND Controller is shown in Table 6.
TABLE 6: Task File Registers
NAND Controller Registers
The following section describes the hardware registers used by the host software to issue commands to the NAND Control-
ler. These registers are often collectively referred to as the Task File registers. The registers are only selectable through
CS3FX#, CS1FX#, and A
Data Register (Read/Write) This 16-bit register is used to transfer data blocks between the device data buffer and the
host. Data transfer can be performed in PIO mode or DMA mode.
Error Register (Read Only) This register contains additional information about the source of an error when an error is
indicated in bit 0 of the Status register. The bits are defined as follows:
©2010 Greenliant Systems, Ltd.
CS3FX#
1
1
1
1
1
1
1
1
0
CS1FX#
Symbol
ICRC / BBK
UNC
IDNF
ABRT
AMNF
ICRC/BBK
0
0
0
0
0
0
0
0
1
D7
A2
2
0
0
0
0
1
1
1
1
1
-A
UNC
Function
This bit is set when a Bad Block is detected. During an ultra-DMA transfer, this bit is set
on detection of a CRC error.
This bit is set when an Uncorrectable Error is encountered.
The requested sector ID is in error or cannot be found.
This bit is set if the command has been aborted because of an NAND Controller status
condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued. It
is required that the host retry any media access command (such as Read-Sectors and
Write-Sectors) that ends with an error condition.
This bit is set in case of a general error.
0
D6
signals.
A1
0
0
1
1
0
0
1
1
1
D5
0
A0
0
1
0
1
0
1
0
1
0
IDNF
D4
IORD# = 0 (IOWR#=1)
Data (Read)
Error
Sector Count
Sector Number (LBA 7-0)
Cylinder Low (LBA 15-8)
Cylinder High (LBA 23-16)
Drive/Head
Status
Alternate Status
16
D3
0
ABRT
D2
Registers
IOWR# = 0 (IORD#=1)
Data (Write)
Feature
Sector Count
Sector Number (LBA 7-0)
Cylinder Low (LBA 15-8)
Cylinder High (LBA 23-16)
Drive/Head
Command
Device Control
D1
0
NAND Controller
AMNF
D0
S71355-05-000
GLS55VD020
Reset Value
0000 0000b
T0-0.0 1355
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