GLS36VF3204-70-4I-B3KE Greenliant, GLS36VF3204-70-4I-B3KE Datasheet - Page 4

• Manufacturer Part Number: GLS36VF3204-70-4I-B3KE
• Description: Flash 2Mx16 or 4Mx8 70ns Industrial Temp
• Manufacturer: Greenliant

Specifications of GLS36VF3204-70-4I-B3KE

• Rohs: yes
• Data Bus Width: 8 bit, 16 bit
• Memory Type: Flash
• Memory Size: 32 Mbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Interface Type: Parallel
• Access Time: 70 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 15 mA
• Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TFBGA-48
• Organization: 4 KB x 1024

Data Sheet
Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output sig-
nal. RY/BY# is an open drain output pin that indicates
whether an Erase or Program operation is in progress.
Since RY/BY# is an open drain output, it allows several
devices to be tied in parallel to V
resistor. After the rising edge of the final WE# pulse in the
command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
Byte/Word (BYTE#)
The device includes a BYTE# pin to control whether the
device data I/O pins operate x8 or x16. If the BYTE# pin is
at logic “1” (V
data I/0 pins DQ
and OE#.
If the BYTE# pin is at logic “0”, the device is in x8 data con-
figuration: only data I/O pins DQ
trolled by CE# and OE#. The remaining data pins DQ
DQ
input A
Data# Polling (DQ
When the devices are in an internal Program operation,
any attempt to read DQ
the true data. Once the Program operation is completed,
DQ
any attempt to read DQ
nal Erase operation is completed, DQ
The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block-, or Chip-Erase, the Data# Polling is valid after the ris-
ing edge of sixth WE# (or CE#) pulse. See Figure 7 for
Data# Polling (DQ
flowchart.
©2010 Greenliant Systems, Ltd.
14
7
will produce true data. During internal Erase operation,
are at Hi-Z, while pin DQ
-1
for the Least Significant Bit of the address bus.
IH
) the device is in x16 data configuration: all
0
-DQ
7
) timing diagram and Figure 21 for a
15
7
7
7
are active and controlled by CE#
will produce a ‘0’. Once the inter-
)
will produce the complement of
15
0
DD
-DQ
is used as the address
via an external pull-up
7
7
are active and con-
will produce a ‘1’.
8
-
4
Toggle Bits (DQ
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or CE#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ
rising edge of sixth WE# (or CE#) pulse. DQ
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ
toggle.
An additional Toggle Bit is available on DQ
used in conjunction with DQ
sector is being actively erased or erase-suspended. Table
1 shows detailed status bit information. The Toggle Bit
(DQ
pulse of a Write operation. See Figure 8 for Toggle Bit tim-
ing diagram and Figure 21 for a flowchart.
TABLE 1: Write Operation Status
Note: DQ
32 Mbit Concurrent SuperFlash
Status
Normal
Operation
Erase-
Suspend
Mode
2
) is valid after the rising edge of the last WE# (or CE#)
status information. The address must be in the bank where
the operation is in progress in order to read the operation sta-
tus. If the address is pointing to a different bank (not busy),
the device will output array data.
7,
DQ
Standard
Program
Standard
Erase
Read From
Erase
Suspended
Sector/Block
Read From
Non-Erase
Suspended
Sector/Block
Program
6,
and DQ
GLS36VF3203 / GLS36VF3204
2
6
require a valid address when reading
and DQ
DQ7#
DQ7#
Data
DQ
0
1
7
6
6
to check whether a particular
will produce alternating “1”s
Toggle
Toggle
Toggle
Data
DQ
1
2
6
)
No Toggle
S71270-05-000
6
Toggle
Toggle
) is valid after the
Data
DQ
N/A
2
, which can be
6
2
will be set to
RY/BY#
6
T1.1 1270
bit will
0
0
1
1
0
6
05/10
will