MAX4031EEUD-T Maxim Integrated, MAX4031EEUD-T Datasheet - Page 7

• Manufacturer Part Number: MAX4031EEUD-T
• Description: High Speed Operational Amplifiers
• Manufacturer: Maxim Integrated

Specifications of MAX4031EEUD-T

• Number Of Channels: 3
• Voltage Gain Db: 80 dB
• Input Offset Voltage: 13 mV at 5 V
• Slew Rate: 115 V/us at 5 V
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TSSOP-14
• Common Mode Rejection Ratio (min): 50 dB
• Gain Bandwidth Product: 144 MHz
• Maximum Power Dissipation: 727 mW
• Minimum Operating Temperature: - 40 C
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

Figure 2. Inverting Gain Configuration
decrease bandwidth or cause oscillations. For exam-
ple, a noninverting gain-of-two configuration (R
using 2k
input capacitance and 1pF of PC board capacitance,
cause a pole at 79.6MHz. Since this pole is within the
amplifier bandwidth, it jeopardizes stability. Reducing
the 2k
to 1.59GHz, but could limit output swing by adding
200
(Figures 1 and 2).
These amplifiers operate from a single 5V power sup-
ply. Bypass V
close to V
microstrip and stripline techniques to obtain full band-
width. To ensure that the PC board does not degrade
the amplifier’s performance, design it for a frequency
greater than 1GHz. Pay careful attention to inputs and
outputs to avoid large parasitic capacitance. Under all
conditions observe the following design guidelines:
•
•
•
Figure 1. Noninverting Gain Configuration
Do not use wire-wrap boards. Wire-wrap boards are
too inductive.
Do not use IC sockets. Sockets increase parasitic
capacitance and inductance.
Use surface mount instead of through-hole compo-
nents for better high-frequency performance.
in parallel with the amplifier’s load resistor
Layout and Power-Supply Bypassing
resistors to 100
IN
CC
resistors, combined with 4pF of amplifier
CC
as possible. Maxim recommends using
IN_+
R
R
G
G
to ground with a 0.1µF capacitor as
_______________________________________________________________________________________
Low-Cost, 144MHz, Dual/Triple Op Amps
MAX403_E
MAX403_E
V
extends the pole frequency
R
R
OUT
V
F
F
OUT
= -(R
= [1+ (R
F
/ R
F
G
V
V
) V
OUT_
/ R
OUT_
IN
G
)] V
IN_+
R
150
L
R
150
L
F
= R
with ±15kV ESD Protection
G
)
•
•
The MAX4030E/MAX4031E are optimized for AC perfor-
mance and do not drive highly reactive loads, which
decreases phase margin and can produce excessive
ringing and oscillation. Figure 3 shows a circuit modifi-
cation that uses an isolation resistor (R
this problem. Figure 4 shows a graph of the Optimal
Isolation Resistor (R
shows how a capacitive load causes excessive peak-
ing of the amplifier’s frequency response if the capaci-
tor is not isolated from the amplifier by a resistor. A
small isolation resistor (usually 10
before the reactive load prevents ringing and oscilla-
tion. At higher capacitive loads, the interaction of the
load capacitance and the isolation resistor controls the
AC performance. Figure 6 shows the effect of a 10
isolation resistor on closed-loop response.
As with all Maxim devices, ESD protection structures
are incorporated on all pins to protect against ESD
encountered during handling and assembly. Input and
output pins of the MAX4030E/MAX4031E have extra
protection against static electricity. Maxim’s engineers
have developed state-of-the-art structures enabling
these pins to withstand ESD up to ±15kV without dam-
age when placed in the test circuit (Figure 7). The
MAX4030E/MAX4031E are characterized for protection
to the following limits:
•
•
•
Figure 3. Driving a Capacitive Load Through an Isolation Resistor
Use a PC board with at least two layers. The PC
board should be as free from voids as possible.
Keep signal lines as short and as straight as possi-
ble. Do not make 90° turns; round all corners.
±15kV using the Human Body Model
±8kV using the Contact Discharge method speci-
fied in IEC 1000-4-2
±15kV using the Air-Gap Discharge method speci-
fied in IEC 1000-4-2
Output Capacitive Loading and Stability
V
IN_+
MAX403_E
ISO
24
R
) vs. Capacitive Load. Figure 5
F
R
ISO
ESD Protection
ISO
to 15 ) placed
C
L
) to eliminate
V
OUT_
7