MAX98090BEWJ+T Maxim Integrated, MAX98090BEWJ+T Datasheet - Page 103

• Manufacturer Part Number: MAX98090BEWJ+T
• Description: Interface - CODECs 5V 130mW Stereo Headphone Amp
• Manufacturer: Maxim Integrated

MAX98090
In master mode, the device provides three clock operating
modes. In reality all three modes operate in exactly the
same manner (using an internal MI and NI ratio to create
LRCLK). However, the first two modes will internally set
NI and MI automatically and are provided as configura-
tion shortcuts for commonly used PCLK to LRCLK ratios.
The three operating modes are detailed below, and are
presented in order of activation priority.
Quick Configuration Mode
In quick configuration mode, the master clock frequency
(Table 36) and sample rate (Table 37) are selected from
a list of commonly used frequencies. Only a single bit in
each quick setup register can be enabled at any given
time. Quick configuration mode is activated anytime
that both a master clock frequency quick setup bit and
Table 36. Master Clock Quick Setup Register
Table 37. Sample Rate Quick Setup Register
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BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
11P2896M
12P288M
SR_44K1
ADDRESS: 0x04
ADDRESS: 0x05
SR_96K
SR_32K
SR_48K
SR_16K
19P2M
SR_8K
NAME
256F
NAME
26M
13M
12M
—
—
—
S
TYPE POR
TYPE POR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
Setup clocks and filters for a 96kHz sample rate.
Setup clocks and filters for a 32kHz sample fate.
Setup clocks and filters for a 48kHz sample rate.
Setup clocks and filters for a 44.1kHz sample rate.
Setup clocks and filters for a 16kHz sample rate.
Setup clocks and filters for an 8kHz sample rate.
Setup device for operation with a 26MHz master clock (MCLK).
Setup device for operation with a 19.2MHz master clock (MCLK).
Setup device for operation with a 13MHz master clock (MCLK).
Setup device for operation with a 12.288MHz master clock (MCLK).
Setup device for operation with a 12MHz master clock (MCLK).
Setup device for operation with a 11.2896MHz master clock (MCLK).
Setup device for operation with a 256 x f
a sample rate quick setup bit are concurrently enabled.
Once enabled, this mode supersedes both of the other
operating modes and an internal preset ratio for NI and
MI is used to create LRCLK. As a result, when Quick
Configuration Mode is enabled the exact integer mode
settings (Table 32), and the manual ratio mode settings
(Tables 33 to 36) are preserved but ignored. If this mode
is later disabled, the preserved settings of any active
lower precedence modes reassert.
To ensure that the DSP is optimally configured and that all
timing requirements are met, when using quick configura-
tion mode the master clock divider (PSCLK, Table 34),
digital filters (MODE, Table 27), and ADC oversampling
rate (OSR128,Table 5) are automatically configured.
While in quick configuration mode these registers are
Ultra-Low Power Stereo Audio Codec
DESCRIPTION
DESCRIPTION
S
MHz master clock (MCLK)
—
—
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