CAT9554AHV4I-GT2 ON Semiconductor, CAT9554AHV4I-GT2 Datasheet - Page 5

• Manufacturer Part Number: CAT9554AHV4I-GT2
• Description: Interface - I/O Expanders 8B I2C/SMBUS I/O PT W/INT
• Manufacturer: ON Semiconductor

Specifications of CAT9554AHV4I-GT2

• Product Category: Interface - I/O Expanders
• Rohs: yes
• Logic Family: CAT9554A
• Number Of I/os: 8
• Maximum Operating Frequency: 400 KHz
• Operating Supply Voltage: 2.3 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-16
• Interface Type: I2C, SMBus
• Interrupt Output: Yes
• Operating Current: 104 uA
• Output Current: 3 mA
• Power Dissipation: 1 W
• Product Type: I/O Expanders

Pin Description
SCL: Serial Clock
of the device. The SCL line requires a pull−up resistor if it
is driven by an open drain output.
SDA: Serial Data/Address
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs. A pull−up resistor must be connected
from SDA line to V
can be calculated based on minimum and maximum values
from Figure 3 and Figure 4 (see Note).
NOTE:
The serial clock input clocks all data transferred into or out
The bidirectional serial data/address pin is used to transfer
SDA OUT
2.5
2.0
1.5
1.0
0.5
SDA IN
0
SCL
According to the Fast Mode I
loads between 200 pF and 400 pF, the pull−up device can be a current source (Imax = 3 mA) or a switched resistor circuit.
2.0
I
OL
= 3 mA @ V
2.4
t
SU:STA
Figure 3. Minimum R
2.8
CC
. The value of the pull−up resistor, R
OLmax
3.2
Supply Voltage
t
F
3.6
V
CC
(V)
2
4.0
C bus specification, for bus capacitance up to 200 pF, the pull up device can be a resistor. For bus
t
HD:STA
t
LOW
P
4.4
Value vs.
Figure 2. I
t
AA
4.8
t
HD:DAT
t
HIGH
5.2
http://onsemi.com
2
C Serial Interface Timing
5.6
P
,
t
LOW
5
t
A0, A1, A2: Device Address Inputs
The A0, A1, A2 pins should be hardwired to V
When hardwired, up to eight CAT9554/9554As may be
addressed on a single bus system. The levels on these inputs
are compared with corresponding bits, A2, A1, A0, from the
slave address byte.
I/O
The simplified schematic of I/O
Figure 5. When an I/O is configured as an input, the Q1 and
Q2 output transistors are off creating a high impedance input
with a weak pull−up resistor (typical 100 kW). If the I/O pin
is configured as an output, the push−pull output stage is
enabled. Care should be taken if an external voltage is
applied to an I/O pin configured as an output due to the low
impedance paths that exist between the pin and either V
or V
DH
These inputs are used for extended addressing capability.
Any of these pins may be configured as input or output.
0
8
7
6
5
4
3
2
1
0
t
SS
to I/O
SU:DAT
0
t
R
.
7
50
: Input / Output Ports
Figure 4. Maximum R
100
150
Bus Capacitance
C
200
BUS
t
t
SU:STO
BUF
(pF)
250
0
to I/O
P
Fast Mode I
300
Value vs.
tr max − 300 ns
7
350
is shown in
2
CC
C Bus /
400
or V
SS
CC
.