MC100EPT21DR2G ON Semiconductor, MC100EPT21DR2G Datasheet - Page 2

no-image

MC100EPT21DR2G

Manufacturer Part Number
MC100EPT21DR2G
Description
IC XLATOR LVPECL-LVTTL 8-SOIC
Manufacturer
ON Semiconductor
Series
100EPTr
Datasheet

Specifications of MC100EPT21DR2G

Logic Function
Translator
Number Of Bits
1
Input Type
CML, LVDS, LVPECL
Output Type
LVTTL, LVCMOS
Number Of Channels
1
Number Of Outputs/channel
1
Differential - Input:output
Yes/No
Propagation Delay (max)
1.8ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Supply Voltage
3 V ~ 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC100EPT21DR2G
Manufacturer:
ON Semiconductor
Quantity:
1 950
Part Number:
MC100EPT21DR2G
Manufacturer:
ON/安森美
Quantity:
20 000
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 3. MAXIMUM RATINGS
V
V
I
T
T
q
q
q
q
q
T
q
Figure 1. Logic Diagram and 8−Lead Pinout (Top View)
Symbol
BB
A
stg
JA
JC
JA
JC
JA
sol
JC
CC
IN
V
NC
BB
D
D
1
2
3
4
PECL Power Supply
PECL Input Voltage
V
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Wave Solder
Thermal Resistance (Junction−to−Case)
BB
Sink/Source
LVPECL
1. For additional information, see Application Note AND8003/D.
Table 2. ATTRIBUTES
Internal Input Pulldown Resistor
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Parameter
LVTTL
Characteristics
Pb−Free
8
7
6
5
V
Q
NC
GND
Pb
CC
http://onsemi.com
GND = 0 V
GND = 0 V
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
< 2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
(Note 2)
Oxygen Index: 28 to 34
Charged Device Model
Condition 1
Human Body Model
2
Machine Model
Table 1. PIN DESCRIPTION
* Pin will default to 1/2 of V
Q
D*, D*
V
V
GND
NC
EP
CC
BB
PIN
D, D
V
SO−8
SO−8
SO−8
TSSOP−8
TSSOP−8
TSSOP−8
DFN8
DFN8
DFN8
D
D
I
 V
Condition 2
LVTTL/LVCMOS Output
Differential LVPECL/LVDS/CML Input
Positive Supply
Output Reference Voltage
Ground
No Connect
(DFN8 only) Thermal exposed pad must be
connected to a sufficient thermal conduit. Elec-
trically connect to the most negative supply
(GND) or leave unconnected, floating open.
CC
UL 94 V−0 @ 0.125 in
81 Devices
> 1.5 kV
CC
> 100 V
Level 1
> 2 kV
50 kW
50 kW
50 kW
Value
FUNCTION
when left open.
−65 to +150
−40 to +85
41 to 44
41 to 44
35 to 40
0 to 3.8
Rating
± 0.5
190
130
185
140
129
265
265
3.8
84
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Unit
mA
°C
°C
°C
V
V

Related parts for MC100EPT21DR2G