FT313HQ-R FTDI, FT313HQ-R Datasheet - Page 25
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FT313HQ-R
Manufacturer Part Number
FT313HQ-R
Description
USB Interface IC USB High Speed USB-- Host Controller IC--
Manufacturer
FTDI
Datasheet
1.FT313HQ-R.pdf
(64 pages)
Specifications of FT313HQ-R
Rohs
yes
Product
USB 2.0
Data Rate
480 Mbps
Interface Type
USB
Operating Supply Voltage
1.62 V to 3.63 V
Operating Supply Current
35 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-64
Minimum Operating Temperature
- 40 C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Bit
1
0
Table 5-6 USB status register
5.2.6 USBINTR register (address = 18h)
This register enables and disables reporting of the corresponding interrupt to the software. When a bit is
set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that
are disabled in this register still appear in the USBSTS to allow the software to poll for events.
Bit
[31:6]
5
4
3
2
1
0
Table 5-7 USB interrupt enable register
Name
Reserved
INT_OAA_EN
H_SYSERR_EN
FRL_ROL_EN
PO_CHG_DET_EN
USBERR_INT_EN
USB_INT_EN
Name
USBERR_INT
USB_INT
Copyright © 2012 Future Technology Devices International Limited
Type
R/WC
R/WC
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
Default value
1’b0
1’b0
FT313H USB2.0 HS Host Controller Datasheet Version 1.1
Default value
26’h0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
Description
the PORTSC change bits.
USB Error Interrupt
The host controller sets this bit to ‘1’ when the
completion of a USB transaction results in an
error condition.
USB Interrupt
The host controller sets this bit to ‘1’ upon the
completion of a USB transaction.
Description
-
Interrupt on Async Advance Enable
When this bit is set to ‘1,’ and the Interrupt on
Async Advance bit in the USBSTS register is
set to ‘1’ also, the host controller will issue an
interrupt at the next interrupt threshold.
Host System Error Enable
When this bit is set to ‘1,’ and the Host
System Error Status bit in the USBSTS register
is set to ‘1’ also, the host controller will issue
an interrupt.
Frame List Rollover Enable
When this bit is set to ‘1,’ and the Frame List
Rollover bit in the USBSTS register is set to ‘1’
also, the host controller will issue an interrupt.
Port Change Interrupt Enable
When this bit is set to ‘1,’ and the Port Change
Detect bit in the USBSTS register is set to ‘1’
also, the host controller will issue an interrupt.
USB Error Interrupt Enable
When this bit is set to ‘1,’ and the USBERRINT
bit in the USBSTS register is set to ‘1’ also, the
host controller will issue an interrupt at the
next interrupt threshold.
USB Interrupt Enable
When this bit is set to ‘1,’ and the USBINT bit
in the USBSTS register is a set to ‘1’ also, the
host controller will issue an interrupt at the
next interrupt threshold. If set interrupt
threshold to 01h, means that when interrupt
event occurred, the INT signal will be toggled
at once.
Document No.: FT_000589
Clearance No.: FTDI# 318
25