MAX3681EAG-T Maxim Integrated, MAX3681EAG-T Datasheet - Page 6

• Manufacturer Part Number: MAX3681EAG-T
• Description: Serializers & Deserializers - Serdes 3.3V 622Mbps SDH/ SONET 1
• Manufacturer: Maxim Integrated
• Type: Deserializerr

Specifications of MAX3681EAG-T

• Data Rate: 622 Mbit/s
• Input Type: LVDS
• Output Type: LVDS
• Number Of Inputs: 1
• Number Of Outputs: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: SSOP-24
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

The MAX3681 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 250mVp-p to 400mVp-p, dif-
ferential low-voltage swings to achieve fast transition
times, minimized power dissipation, and noise immunity.
The parallel clock and data LVDS outputs (PCLK+,
PCLK-, PD_+, PD_-) require 100Ω differential DC termi-
nation between the inverting and noninverting outputs
for proper operation. Do not terminate these outputs to
ground.
The synchronization LVDS inputs (SYNC+, SYNC-) are
internally terminated with 100Ω of differential input
resistance, and therefore do not require external termi-
nation.
The serial data and clock PECL inputs (SD+, SD-,
SCLK+, SCLK-) require 50Ω termination to (V
when interfacing with a PECL source (see the
Alternative PECL Input Termination section).
Figure 4 shows alternative PECL input-termination
methods. Use Thevenin-equivalent termination when a
(V
coupling is necessary, such as when interfacing with
an ECL-output device, use the ECL AC-coupling termi-
nation.
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3681 data inputs and outputs.
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
6
__________Applications Information
CC
_______________________________________________________________________________________
Low-Voltage Differential-Signal (LVDS)
- 2V) termination voltage is not available. If AC
Alternative PECL Input Termination
Inputs and Outputs
Layout Techniques
PECL Inputs
CC
- 2V)
Figure 4. Alternative PECL Input Termination
Z
Z
O
O
= 50Ω
= 50Ω
+3.3V
+3.3V
Z
Z
O
O
= 50Ω
= 50Ω
-2V
-2V
THEVENIN-EQUIVALENT TERMINATION
ECL AC-COUPLING TERMINATION
50Ω
130Ω
50Ω
1.6k
82Ω
2.7k
130Ω
1.6k
82Ω
2.7k
PECL
INPUTS
PECL
INPUTS
MAX3681
MAX3681