MAX3107EVKIT+ Maxim Integrated, MAX3107EVKIT+ Datasheet - Page 16
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MAX3107EVKIT+
Manufacturer Part Number
MAX3107EVKIT+
Description
UART Interface IC UART with integrated Oscillator
Manufacturer
Maxim Integrated
Datasheet
1.MAX3107ETGV.pdf
(52 pages)
Specifications of MAX3107EVKIT+
Number Of Channels
1
Data Rate
24 Mbps
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.71 V
Supply Current
4 mA
MAX3107
16
Figure 4. Receive Data Format
Figure 5. Midbit Sampling
SPI/I
To halt transmission, set MODE1[1]: TxDisabl to 1. After
MODE1[1] is set, the transmitter completes transmission
of the current character and then ceases transmission.
The TX output logic can be inverted through IrDA[5]:
TxInv. If not stated otherwise, all transmitter logic
described in this data sheet assumes IrDA[5] is 0.
The receiver expects the format of the data at RX to be
as shown in Figure 4. The quiescent logic state is a high
and the first bit (the START bit) is logic-low. The receiver
samples the data near the midbit instant (Figure 4). The
received words and their associated errors are depos-
ited into the receive FIFO. Errors and status information
are stored for every received word (Figure 6). The host
reads data out of the receive FIFO through the Receive
Holding register (RHR), oldest data first. The status
information of the word previously read out of the RHR is
located in the Line Status register (LSR). After a word is
read out of the RHR, the LSR contains the status informa-
tion for that word.
The following three error conditions are determined for
each received word: parity error, framing error, and
noise on the line. Line noise is detected by checking the
consistency of the logic of the three samples (Figure 5).
The receiver can be turned off through MODE1[0]:
RxDisabl. When this bit is set to 1, the MAX3107 turns the
receiver off immediately following the current word and
RECEIVED DATA
BLOCK
BAUD
SAMPLING
RX
MIDBIT
2
C UART with 128-Word FIFOs
A
1
START
2
3
Receiver Operation
LSB
D0
4
D1
5
6
D2
7
D3
8
ONE BIT PERIOD
does not receive any further data. The RX input logic can
be inverted through IrDA[4]: RxInv.
When operating in standard (i.e., not 2x or 4x rate) mode,
the MAX3107 checks that the binary logic level of the
three samples per received bit are identical. If any of
the three samples have differing logic levels, then noise
on the transmission line has affected the received data
and is considered to be noisy. This noise indication is
reflected in the LSR[5]: RxNoise bit for each received
byte. Parity errors are another indication of noise, but are
not as sensitive.
The MAX3107 can be clocked by an external crystal or an
external clock source. Figure 7 shows a simplified diagram
of the clocking circuitry. When the MAX3107 is clocked
by the crystal, the STSInt[5]: ClockReady indicates when
the clocks have settled and the baud-rate generator is
ready for stable operation.
The baud-rate clock can be routed to the RTS/CLKOUT
output. The clock rate is 16x the baud rate in standard
operating mode, and 8x the baud rate in 2x rate mode.
In 4x rate mode, the CLKOUT frequency is 4x the
programmed baud rate. If the fractional portion of the
baud-rate generator is used, the clock is not regular and
exhibits jitter.
9
D4
10
MAJORITY
SAMPLER
CENTER
D5
Clocking and Baud-Rate Generation
11
D6
12
13
MSB
D7
14
Line Noise Indication
PARITY
15
16
STOP
Maxim Integrated
STOP