DS2165QL Maxim Integrated, DS2165QL Datasheet
DS2165QL
Specifications of DS2165QL
Related parts for DS2165QL
DS2165QL Summary of contents
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... Single +5V supply; low-power CMOS technology § Available in 28-pin PLCC § 3V operation version is available (DS2165QL) DESCRIPTION The DS2165Q ADPCM processor chip is a dedicated digital-signal-processing (DSP) chip that has been optimized to perform adaptive-differential pulse-code modulation (ADPCM) speech compression at three different rates. The chip can be programmed to compress (expand) 64kbps voice data down to (up from) either 32kbps, 24kbps, or 16kbps ...
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OVERVIEW The DS2165Q contains three major functional blocks: a high performance (10 MIPS) DSP engine, two independent PCM interfaces (X and Y) that connect directly to serial time-division-multiplexed (TDM) backplanes, and a serial port that can configure the device on-the-fly ...
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... Y Frame Sync. 8kHz frame sync for the Y-side PCM interface. Y Data Clock. Data clock for the Y-side PCM interface; must be synchronous with FSY. Y Data In. Sampled on falling edge of CLKY during selected time slots. Positive Supply. 5.0V (3.0V for DS2165QL for normal operation select the serial port; connect to V ...
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Figure 1. BLOCK DIAGRAM Figure 2. SERIAL PORT WRITE Note: A 2-byte write is shown. The bypass feature is enabled when BYP is set and IPD is cleared. During bypass, no expansion or compression occurs. Bypass operates on bytewide (8 ...
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Figure 3. ADDRESS/COMMAND BYTE (MSB) — SYMBOL POSITION — ACB.7 ACB ACB.5 A4 ACB.4 A3 ACB.3 A2 ACB.2 A1 ACB.1 A0 ACB.0 Figure 4. CONTROL REGISTER (MSB) AS0 AS1 SYMBOL POSITION AS0 CR.7 AS1 CR.6 ...
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Table 2. ALGORITHM SELECT BITS ALGORITHM SELECTED 64kbps to/from 32kbps 64kbps to/from 24kbps 64kbps to/from 16kbps Figure 5. INPUT TIME SLOT REGISTER (MSB) — —- SYMBOL POSITION — ITR.7 — ITR.6 D5 ITR.5 D4 ITR.4 D3 ITR.3 D2 ITR.2 D1 ...
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TIME SLOT ASSIGNMENT/ORGANIZATION On-board counters establish when PCM and ADPCM I/O occur. The counters are programmed by the time slot registers. Time slot size (number of bits wide) is determined by the state of CP/ of time slots available is ...
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Figure 9. A-LAW PCM INTERFACE Figure 10. A-LAW ADPCM INTERFACE DS2165Q ...
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HARDWARE MODE The hardware mode is intended for applications that do not have an external controller available or do not require the extended features offered by the serial port. Connecting the SPS pin to V port, clears all internal register ...
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Table 4. ALGORITHM SELECT FOR HARDWARE MODE ALGORITHM 64kbps to/from 32kbps Connect both A1 and Hold A1 and A4 low during a hardware reset; take both A1 and A4 high after the 64kpbs to/from 24kbps has returned ...
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PCM AND ADPCM INPUT/OUTPUT Since the organization of the input and output time slots on the DS2165Q does not depend on the algorithm selected, it always assumes that PCM input and output are in 8-bit bytes and that ADPCM input ...
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TIME SLOT RESTRICTIONS Under certain conditions, the DS2165Q does contain some restrictions on the output time slots that are available. These restrictions are covered in detail in a separate application note. No restrictions occur if the DS2165Q is operated in ...
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... +0 +0 TYP MAX UNITS ±10 0°C to +70° 3.0V + 20% - 10% for DS2165QL) TYP MAX UNITS +1 DS2165Q NOTES +25°C) NOTES NOTES ...
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... WMH 45 t WML RST 3.0V + 20% - 10% for DS2165QL) DD TYP MAX UNITS 3906 150 ns 150 ns = 3.0V + 20% - 10% for DS2165QL) DD TYP MAX UNITS 100 DS2165Q NOTES NOTES 1 ...
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... CDH t 250 CL t 250 250 CCH t 250 CWH t 50 SCC = 0.8V, and 10ns maximum rise and fall times 3.0V + 20% - 10% for DS2165QL) DD TYP MAX UNITS 100 DS2165Q NOTES ...
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Figure 13. PCM INTERFACE AC TIMING DIAGRAM Figure 14. MASTER CLOCK/RESET AC TIMING DIAGRAM Figure 15. SERIAL PORT AC TIMING DIAGRAM Note: SCLK can be either high or low when CS is taken low DS2165Q ...
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PLCC INCHES DIM MIN MAX A 0.165 0.180 A1 0.090 0.120 A2 0.020 — B 0.026 0.033 B1 0.013 0.021 C 0.009 0.012 D 0.485 0.495 D1 0.450 0.456 D2 0.390 0.430 E 0.485 0.495 E1 0.450 0.456 E2 ...