MAX7469UTP Maxim Integrated, MAX7469UTP Datasheet - Page 9

• Manufacturer Part Number: MAX7469UTP
• Description: Video ICs
• Manufacturer: Maxim Integrated

MAX7469 when driving an ADC or video decoder with an
input range the same as the input to the MAX7469. For
added flexibility, the MAX7469 accepts input signals with
twice the standard video-signal range, which can be
used for driving an ADC or video decoder with an input
signal range that accepts a larger signal swing. The
MAX7470 can also be used to drive an ADC or video
decoder when a gain of two is desired.
The MAX7469/MAX7470 output can be DC- or AC-
coupled. The nominal output clamp level in the
DC-coupled case depends on the clamp voltage set-
ting and can be determined according to Table 2.
As shown in the Sync Detector and Clamp Settings
section, the low clamp level is used for signals with
sync information and determines the voltage level of the
sync tip, while the high clamp level is used for signals
without sync information and sets the blanking level.
The absolute voltage level of the output signal is rela-
tive to the output clamp level. A video signal containing
sync information (i.e., CVBS or Y) is unipolar above the
clamp level and conversely, a video signal without sync
(i.e., P
The MAX7469/MAX7470 include a power-down mode
that reduces the supply current from 180mA (typ) to 1mA
(typ) by powering down the analog circuitry. The I
interface remains active, allowing the device to return to
full-power operation. The clamp settling time (see the
Electrical Characteristics section) limits the wake-up time
of the MAX7469/MAX7470. After exiting the power-down
mode, the MAX7469/MAX7470 resume normal operation
using the settings stored prior to power-down. The
power-down and wake-up modes are controlled through
the command byte (see Table 3). A software reset sets
the control/status register to its default conditions, but
the frequency register is not affected.
Table 2. Output Clamp Level
CLAMP SETTING
b
High
Low
P
r
or C) is bipolar around the clamp level.
_______________________________________________________________________________________
OUTPUT CLAMP LEVEL (V)
Power-Down Mode
1.0 (typ)
1.6 (typ)
Output Clamp Level
HDTV Continuously Variable
2
C
The MAX7469/MAX7470 include a POR circuit that
resets the internal registers and I
default conditions (see Tables 4, 5, and 6).
The MAX7469/MAX7470 feature an I
serial interface consisting of a bidirectional serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facilitate
bidirectional communication between the MAX7469/
MAX7470 and the master at rates up to 400kHz.
The MAX7469/MAX7470 have a command interpreter
that is accessed by writing a valid command byte.
Once a command byte is written to the MAX7469/
MAX7470, the command interpreter updates the con-
trol/status register accordingly. See the Control/Status
Register section for more information. The command
interpreter also controls access to the frequency regis-
ter through a command byte (see the Command Byte
( Write Cycle) section).
The MAX7469/MAX7470 are transmit/receive slave-only
devices, relying upon a master to generate a clock sig-
nal. The master (typically a µC) initiates data transfer on
the bus and generates SCL.
A master device communicates to the MAX7469/
MAX7470 by transmitting the proper address (see the
Slave Address section) followed by a command and/or
data words. Each transmit sequence is framed with a
START (S) or REPEATED START (Sr) condition and a
STOP (P) condition.
The SDA driver is an open-drain output, requiring a
pullup resistor (2.4kΩ or greater) to generate a logic-
high voltage. Optional resistors (24Ω) in series with
SDA and SCL protect the device inputs from high-volt-
age spikes on the bus lines. Series resistors also mini-
mize crosstalk and undershoot of the bus signals.
Each SCL rising edge transfers 1 data bit. Nine clock
cycles are required to transfer the data into or out of the
MAX7469/MAX7470. The data on SDA must remain stable
during the high period of the SCL clock pulse. Changes in
SDA while SCL is high are read as control signals (see the
START and STOP Conditions section). When the serial
interface is inactive, SDA and SCL idle high.
Anti-Aliasing Filters
Power-On Reset (POR)
2
2
Serial Interface
C-compatible, 2-wire
C interface to their
Bit Transfer
9