E981.12A39BB ELMOS Semiconductor, E981.12A39BB Datasheet - Page 33

• Manufacturer Part Number: E981.12A39BB
• Description: Interface - Specialized Dual I/O Link Master Transciever
• Manufacturer: ELMOS Semiconductor

Specifications of E981.12A39BB

• Rohs: yes
• Product Type: Dual I/O link Master Transceiver
• Operating Supply Voltage: 3.3 V
• Supply Current: 5.5 mA
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-44
• Minimum Operating Temperature: - 40 C

Dual IO-Link Master Transceiver with UARTS
ADVANCE PRODUCT INFORMATION - JUL 26, 2011
6.4
The oscillator provides the clock for internal and external digital circuitry. The required oscillator
accuracy depends on the application concept.
In applications using the parallel communication interface (TXEN, TXD, RXD) the external
microcontroller provides the needed bit time accuracy. In this case the internal oscillator (OSC
sufficient for system control and wakeup pulse generation and no external components are needed.
6.4.1
In applications using the internal UARTs and IO-Link cycle timer the system clock accuracy has to be
better than 0.1%. The clock system structure is shown in Fig. 15.
Clock accuracy can be reached by applying either an:


This external signal is used to synchronize the internal PLL block.
If f
signal path. In this case there is no need to configure the CLK_FAC divider.
In case of higher input frequencies f
f
Register CLK_CTRL configures the XTAL input stage.Bit ENX enables the XTAL input/output stage. Bit
EXTQ enables the quartz oscillator. If the quartz oscillator is not needed it can be disabled to reduce
power dissipation.
The CLK_FAC divider has a reset value of 0x1C71 (7281d). Using other quartz frequencies than 7.3728
MHz the CLK_FAC value has to be changed to CLK_FAC = f
The CLK_FAC can be in range of 0x0400 (2048d) up to 0x3FFF (16383d) which allows a wide range of
the input frequency. It is recommended to configure the CLK_FAC registers reset condition of the IO-
LINK Master IC.
This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
ELMOS Semiconductor AG
SYNC
XTAL_IN
XTAL_OUT
external quartz at XTAL_IN and XTAL_OUT. No external capacitors are necessary. To increase the
robustness to EMI the input XTAL_IN shall be connected to GND if the quartz oscillator is not used.
or an digital clock signal from an external clock source provided by an external microcontroller or by
the CLK_OUT signal of other E981.12 devices used in multi port applications.
CLK_OUT
signal. The internal multiplexer automatically switches to this signal path.
XTAL_IN
Oscillator
it is excatly f
PLL
SYNC
= 1.0125 kHz the multiplexer automatically switches directly to the XTAL_IN
OSC
Q
Fig. 15: Clock system structure
XTAL_IN
CLKOEN
is divided by the CLK_FAC divider block to get the 1.0125 kHz
CLK
Data Sheet 33 / 44
Q
Divider
CLK_FAC
OSC
RC
Quartz
f
8 Mhz
RC
/ C
sync
- 1
PLL
f
1.0125 kHz
±0.02%
SYNC
QM-No.: 25DS0069E.00
f
2.0736 Mhz
±0.1%
E981.12
SYS
RC
) is