A2SI-L14-G1-SR ZMDI, A2SI-L14-G1-SR Datasheet - Page 15

• Manufacturer Part Number: A2SI-L14-G1-SR
• Description: Interface - Specialized ASI
• Manufacturer: ZMDI

Specifications of A2SI-L14-G1-SR

• Rohs: yes
• Product Type: Actuator Sensor Interface IC
• Operating Supply Voltage: 12 V to 31.6 V
• Supply Current: 8.5 mA
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOP-14
• Minimum Operating Temperature: - 25 C

conditions. A small current is required which will be ramped up slowly to avoid any false voltage pulses on the
AS-i line. The amount of circuitry between the ASI+ and ASI- pins is minimized to allow high impedance
values. When the transmitter is turned on the receiver is turned off to reduce the power consumption.
4.5. Digital Logic
The digital logic block analyses the received signal, controls the reaction of the slave, transmits the slave
response and switches the output ports.
Essential parts of the digital logic are as follows:



By setting the Program_Mode_Disable flag (refer to Table C.1 ), the manufacturers of AS-i slave components
may protect the entire firmware area – addresses 0x8 up to 0xC – against accidental overwriting.
The Watchdog_Active flag enables the internal communication watchdog. Once the communication was
activated, it will trigger an unconditional reset as soon as it detects a data communication pause longer than
40ms. It should be noted that only the reception of a Write Parameter (WPAR) or Data Exchange (DEXG)
master call can reset the watchdog.
Notes:
Data Sheet
October 20, 2011
Table 4.1: A²SI-L Master Calls and Related Slave Responses
Data Exchange
Write Parameter
Address Assignment ADRA
Write Extented ID
Code_1
Delete Address
Reset Slave
Read IO
Configuration
Read ID Code
Read ID Code_1
Read ID Code_2
Read Status
Broadcast (Reset)
Enter Program Mode PRGM
A²SI-Light 14 / A²SI-Light 16
Low End Device AS-Interface
The UART performs a syntactical analysis of the incoming master signal and executes the Manchester-
coding of the outgoing slave answer.
The STATE MACHINE controls the overall behavior of the slave. Depending on the configuration data
provided by the EEPROM and the logic levels at the digital input ports it computes the contents of the
slave answer where required. Table 4.1 lists all master calls that will be decoded by the A²SI-L IC.
Moreover, the logic state of the digital output ports is controlled by the STATE MACHINE Chapters 4.6 as
well as 4.7 contain more detailed descriptions of the digital I/O-ports.
The EEPROM stores the non-volatile data of the A²SI-L circuit. A specification of the EEPROM contents is
given in Table C.1 on page 27. The meanings of some configuration flags are explained below and in
Chapter 4.6, respectively.
Instruction
DEXG
WPAR
WID1
DELA
RES
RDIO
RDID
RID1
RID2
RDST
BR01
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 3.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
MNE
ST
0
0
0
0
0
0
0
0
0
0
0
0
0
CB
0
0
0
1
1
1
1
1
1
1
1
1
1
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
0
0
1
0
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
0
0
1
0
Master Request
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
0
0
1
0
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
0
0
1
0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
0
0
1
0
A4
I4
0
1
0
0
1
1
1
1
1
1
1
1
0 Sel
~Sel
~Sel
~Sel
~Sel
ID3
Sel
Sel
Sel
Sel
D3
P3
A3
I3
0
1
1
0
0
0
0
1
ID2
D2
P2
A2
I2
0
1
0
0
0
0
1
1
1
ID1
D1
P1
A1
I1
0
0
0
0
1
1
1
0
0
ID0
D0
P0
A0
I0
0
0
0
1
0
1
0
1
1
PB
PB
PB
PB
PB
PB
PB
PB
PB
PB
PB
PB
PB
PB
EB
1
1
1
1
1
1
1
1
1
1
1
1
1
SB
0
0
0
0
0
0
0
0
0
0
0
--- no slave response ---
--- no slave response ---
P3 I3 P2 I2 P1 I1 P0 I0 PB
IO3 IO2 IO1 IO0
ID3
ID3
ID3
E3
S3
I3
0
0
0
0
0
Slave Response
ID2
ID2
ID2
E2
S2
I2
1
0
0
1
0
ID1
ID1
ID1
D1
E1
S1
I1
1
0
0
1
ID0
ID0
ID0
D0
E0
S0
I0
0
0
0
0
PB
PB
PB
PB
PB
PB
PB
PB
PB
PB
PB
15 of 27
EB
1
1
1
1
1
1
1
1
1
1
1