SAP51C-B-G1-T ZMDI, SAP51C-B-G1-T Datasheet - Page 35

• Manufacturer Part Number: SAP51C-B-G1-T
• Description: Interface - Specialized ASI
• Manufacturer: ZMDI

Specifications of SAP51C-B-G1-T

• Rohs: yes
• Product Type: Actuator Sensor Interface IC
• Operating Supply Voltage: 16 V to 34 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOP-16
• Minimum Operating Temperature: - 25 C

Table 21: Timing Data Port Outputs
Symbol Parameter
t
t
t
t
1
2
3
4.8.2.
D0..D3
Besides the standard input function the Data Port offers different data pre-processing features that can be
activated by setting corresponding flags in the Firmware Area of the E²PROM.

The input values of all four data input channels are inverted if the Invert_Data_In flag is set.

If the Delay Mode is activated, a new input value is returned to the master if equal input data was sampled for
two consecutive Data_Exchange cycles. As long as the condition is not true, previous valid data is returned.
To suppress undesired input data validation in case of immediately repeated Data_Exchange calls (i. e. AS-i
Masters immediately repeat one Data_Exchange requests if no valid slave response was received on the first
request) input data sampling is blocked for 256µs (-6.25%) after every sampling event.
Data Sheet
October 20, 2011
DSTBn
STB
hold
DSTBn
DI-latch
Parameter is only valid if the respective data port is configured as I/O pin.
The timing of the resulting voltage signal also depends on the external pull up resistor.
The input data must be stable within the period defined by min. and max. values of t
SAP5S / SAP51
Universal Actuator-Sensor Interface IC
Input Inverting
Input Delay
Input Data Pre-Processing
Output data is valid after DSTBn HIGH/LOW edge
Output driver is at high impedance state after DSTBn LOW/HIGH
Pulse width of Data Strobe (DSTBn)
Acceptance of input data
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 3.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
Figure 7: Timing diagram data port D0 ... D3 and DSTBn
t
STB
data port output data
t
DSTBn
t
DI-latch
t
hold
min
data port input data
10.5
Min
0.0
0.2
6.0
keep stable
max
12.5
DI-latch
Max
1.5
1.0
6.8
.
Unit
µs
µs
µs
µs
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Note
1
2
3