MAX3822UCM+ Maxim Integrated, MAX3822UCM+ Datasheet - Page 7

• Manufacturer Part Number: MAX3822UCM+
• Description: Limiting Amplifiers Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated

Specifications of MAX3822UCM+

• Rohs: yes
• Factory Pack Quantity: 250

Figure 1. Functional Diagram
up to 80mVp-p. This differential amplifier is designed to
work with the power-detect circuitry.
The next high-gain amplifier provides an additional gain
of approximately 22dB. This gain stage functions simi-
larly to the input-gain stage. The output signal from this
gain stage is applied to the CML output buffer shown in
Figure 3, and is used in the offset-correction loop.
The input voltage range is limited to V
ESD structure, and to a minimum of V
internal resistor. Figure 2 shows a model of the input
stage of the MAX3822, including the package capaci-
tance and the bond wire inductance. The additional
0.4pF capacitance on the inputs represents the ESD
diode’s junction capacitance and a small contribution
by the bond pad. For more information about the CML
electrical specifications and interfacing to other proto-
IN1+
IN1-
CS
R
VTH
TH
CHANNEL
SELECT
_______________________________________________________________________________________
BUFF
MAX3822
+3.3V, 2.5Gbps Quad Limiting Amplifier
THRESHOLD
CONTROL
GAIN
OFFSET CORRECTION
CZ1+
LOW PASS
IN2+
CZ1-
CC
IN2-
CC
GAIN
CZ2+
AMPLIFIER
+ 0.5V by the
LIMITING
- 1V by the
#2
CZ2-
OUT2+
OUT2-
LOP2
LOW-PASS FILTER
RECTIFIER AND
IN3+
cols, refer to Application Note HFAN-1.0, Introduction
to LVDS, PECL, and CML.
Be sure the MAX3822 is placed as close as possible to
the TIA when using this device near sensitivity. If you
are using a TIA with CML outputs, such as the
MAX3825, AC-coupling capacitors are not required.
Taking these precautions will ensure the best possible
sensitivity.
The MAX3822’s CML output buffer is designed to drive
50Ω lines that are used to feed the input of a clock- and
data-recovery device (CDR). Figure 3 shows a model of
the output stage showing some important details. The
outputs of the device are terminated internally with 50Ω
to V
and GND. Figure 3 also shows the model of the output
IN3-
CZ3+
CML
AMPLIFIER
CC
LIMITING
LIMITING AMPLIFIER #1
#3
. ESD diode structures are connected to V
CZ3-
OUT3+
OUT3-
LOSS-OF-POWER LOGIC
LOP3
IN4+
IN4-
R
S
CZ4+
AMPLIFIER
LIMITING
Q
#4
CZ4-
OUT4+
LOSS OF POWER
Output Buffer
OUT4-
LOP4
OUT1+
OUT1-
LOP1
LOP
CC
7