IDT74ALVCH16901PAG IDT, Integrated Device Technology Inc, IDT74ALVCH16901PAG Datasheet - Page 2

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IDT74ALVCH16901PAG

Manufacturer Part Number
IDT74ALVCH16901PAG
Description
IC UNIV BUS TXRX 18BIT 64TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
74ALVCHr
Datasheet

Specifications of IDT74ALVCH16901PAG

Logic Type
Universal Bus Transceiver, CMOS
Number Of Circuits
18-Bit
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74ALVCH16901PAG
PIN CONFIGURATION
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
1
2
CLKENAB
CLKENAB
1
CLKAB
2
1
2
ERRA
ERRA
APAR
APAR
OEAB
LEAB
GND
GND
GND
GND
SEL
V
1
1
V
1
1
2
2
1
1
1
1
2
2
2
2
2
2
A
A
A
A
A
A
A
CC
A
A
A
A
A
A
A
A
A
CC
5
6
4
1
7
4
7
8
2
3
8
2
3
5
1
6
12
13
14
15
16
17
18
1
10
11
19
24
2
3
4
5
6
7
8
9
20
21
22
23
25
26
27
28
29
30
31
32
TOP VIEW
TSSOP
64
63
60
59
56
54
53
52
50
49
46
45
44
43
62
61
58
57
55
51
48
47
42
41
40
39
38
37
36
35
34
33
1
1
1
1
GND
1
2
GND
2
2
ODD/EVEN
2
1
1
1
1
2
2
2
V
2
2
GND
2
2
OEBA
CLKBA
1
V
LEBA
GND
1
B
BPAR
B
CLKENBA
ERRB
B
B
B
B
B
B
B
B
B
B
BPAR
ERRB
CLKENBA
B
B
B
B
CC
CC
8
5
6
7
1
2
3
4
6
1
4
5
7
8
2
3
2
CAPACITANCE
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
ABSOLUTE MAXIMUM RATINGS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
2. V
3. All terminals except V
Symbol
V
V
T
I
I
I
I
I
C
Symbol
C
C
CC
OUT
IK
OK
SS
xCLKENAB
xCLKENBA
ODD/EVEN
Pin Names
STG
TERM
TERM
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
IN
OUT
OUT
CC
CLKAB
CLKBA
xAPAR
xBPAR
xERRA
xERRB
OEAB
OEBA
LEAB
LEBA
SEL
x A x
x B x
terminals.
(2)
(3)
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
Continuous Clamp Current, V
Continuous Current through each
V
Input Capacitance
Output Capacitance
I/O Port Capacitance
I
CC
< 0 or V
Parameter
or GND
I
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B 9-bit Clock Enables
B-to-A 9-bit Clock Enables
A-to-B Clock Input
B-to-A Clock Input
A Error-Signal Outputs
B Error-Signal Outputs
A Port Parities
B Port Parities
Parity Select Input
Parity Enables
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
CC
> V
Description
.
CC
(1)
(T
A
INDUSTRIAL TEMPERATURE RANGE
= +25°C, F = 1.0MHz)
Conditions
V
V
V
OUT
Description
IN
IN
O
= 0V
< 0
= 0V
= 0V
–0.5 to V
Typ.
–0.5 to +4.6
–65 to +150
–50 to +50
5
7
7
±100
Max
±50
–50
CC
Max.
+0.5
7
9
9
(1)
(1)
(1)
Unit
Unit
pF
pF
pF
mA
mA
mA
mA
° C
V
V

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