MAX4126ESA-T Maxim Integrated, MAX4126ESA-T Datasheet - Page 13

• Manufacturer Part Number: MAX4126ESA-T
• Description: Operational Amplifiers - Op Amps Dual Wide-Bandwdth Single-Supply R-R
• Manufacturer: Maxim Integrated

Specifications of MAX4126ESA-T

• Number Of Channels: 2
• Common Mode Rejection Ratio (min): 74 dB
• Input Offset Voltage: 750 uV
• Input Bias Current (max): 150 nA
• Operating Supply Voltage: 2.7 V to 6.5 V, +/- 1.35 V to +/- 3.25 V
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Narrow
• Slew Rate: 2 V/us
• Shutdown: No
• Output Current: 50 mA
• Maximum Operating Temperature: + 85 C
• Amplifier Type: Wideband Amplifier
• Gain Bandwidth Product: 5 MHz
• Maximum Dual Supply Voltage: +/- 3.25 V
• Minimum Dual Supply Voltage: +/- 1.35 V
• Minimum Operating Temperature: - 40 C
• Supply Current: 0.65 mA
• Voltage Gain Db: 106 dB

The MAX4122–MAX4129 amplifiers typically settle with-
in 1µs after power-up. Using the test circuit of Figure
10, Figures 11 and 12 show the output voltage and
supply current on power-up.
The MAX4123, MAX4125, and MAX4127 have a shut-
down option. When the shutdown pin (SHDN) is pulled
low, the supply current drops below 25µA per amplifier
and the amplifiers are disabled with the outputs in a
high-impedance state. Pulling SHDN high or leaving it
floating enables the amplifier. In the dual-amplifier
MAX4129, the shutdown functions operate indepen-
dently. Figures 13 and 14 show the output voltage and
supply current responses of the MAX4123 to a shut-
down pulse.
Figure 11. Power-Up Output Voltage
Figure 13. Shutdown Output Voltage
Single/Dual/Quad, Wide-Bandwidth, Low-Power,
(0.5V/div)
(1V/div)
SHDN
V
OUT
OUT
CC
V
R
Power-Up and Shutdown Mode
CC
L
= 10k
= 2.7V
______________________________________________________________________________________
Single-Supply Rail-to-Rail I/O Op Amps
TIME (5 s/div)
TIME (2 s/div)
The MAX4122–MAX4129 operate from a single +2.7V
to +6.5V power supply, or from dual supplies of ±1.35V
to ±3.25V. For single-supply operation, bypass the
power supply with a 0.1µF ceramic capacitor in parallel
with at least 1µF. For dual supplies, bypass each sup-
ply to ground.
Good layout improves performance by decreasing the
amount of stray capacitance at the op amp’s inputs
and outputs. To decrease stray capacitance, minimize
trace lengths and resistor leads by placing external
components close to the op amp’s pins.
Figure 12. Power-Up Supply Current
Figure 14. Shutdown Enable/Disable Supply Current
(500 A/div)
(500 A/div)
(1V/div)
(1V/div)
SHDN
V
I
I
CC
CC
CC
V
CC
= 2.7V
Power Supplies and Layout
TIME (2 s/div)
TIME (5 s/div)
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