MAX4127ESD-T Maxim Integrated, MAX4127ESD-T Datasheet - Page 11

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MAX4127ESD-T

Manufacturer Part Number
MAX4127ESD-T
Description
Operational Amplifiers - Op Amps
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX4127ESD-T

Number Of Channels
2
Common Mode Rejection Ratio (min)
74 dB
Input Offset Voltage
0.75 mV
Input Bias Current (max)
0.15 uA
Operating Supply Voltage
3 V or 5 V
Mounting Style
SMD/SMT
Package / Case
SOIC-14 Narrow
Slew Rate
2 V/us
Shutdown
Yes
Maximum Operating Temperature
+ 85 C
Amplifier Type
Wideband Amplifier
Gain Bandwidth Product
5 MHz
Maximum Dual Supply Voltage
+/- 3.25 V
Minimum Dual Supply Voltage
+/- 1.35 V
Minimum Operating Temperature
- 40 C
Voltage Gain Db
106 dB
Devices in the MAX4122–MAX4129 family of high-
speed amplifiers have rail-to-rail input and output
stages designed for low-voltage single-supply opera-
tion. The input stage consists of separate NPN and
PNP differential stages, which combine to provide an
input common-mode range extending 0.2V beyond the
supply rails. The PNP stage is active for input voltages
close to the negative rail, and the NPN stage is active
for input voltages near the positive rail. The input offset
voltage is typically below 200µV. The switchover transi-
tion region, which occurs near V
extended to minimize the slight degradation in CMRR
caused by the mismatch of the input pairs. Their low
offset voltage, high bandwidth, and rail-to-rail common-
mode range make these op amps excellent choices for
precision low-voltage data-acquisition systems.
Since the input stage switches between the NPN and
PNP pairs, the input bias current changes polarity as
the input voltage passes through the transition region.
To reduce the offset error caused by input bias cur-
rents flowing through external source impedances,
match the effective impedance seen by each input
(Figures 1a, 1b). High source impedances, together
with the input capacitance, can create a parasitic pole
that produces an underdamped signal response.
Reducing the input impedance or placing a small (2pF
to 10pF) capacitor across the feedback resistor
improves the response.
The MAX4122–MAX4129’s inputs are protected from
large differential input voltages by 1kΩ series resistors
and back-to-back triple diodes across the inputs
(Figure 2). For differential input voltages less than 1.8V
the input resistance is typically 500kΩ. For differential
input voltages greater than 1.8V the input resistance is
approximately 2kΩ, and the input bias current is
determined by the following equation:
The minimum output voltage will be within millivolts of
ground for single-supply operation where the load is
referenced to ground (V
voltage range and output voltage swing of a MAX4123
connected as a voltage follower. With a +3V supply
and the load tied to ground, the output swings from
Single/Dual/Quad, Wide-Bandwidth, Low-Power,
Applications Information
I
BIAS
______________________________________________________________________________________
=
Single-Supply Rail-to-Rail I/O Op Amps
Rail-to-Rail Output Stage
EE
Rail-to-Rail Input Stage
V
DIFF
). Figure 3 shows the input
2k
- 1.8V
CC
/ 2, has been
0.00V to 2.90V. The maximum output voltage swing
depends on the load, but will be within 150mV of a +3V
supply, even with the maximum load (500Ω to ground).
Driving a capacitive load can cause instability in most
high-speed op amps, especially those with low quiescent
current. The MAX4122–MAX4129 have a high tolerance
for capacitive loads. They are stable with capacitive
loads up to 500pF. Figure 4 gives the stable operating
region for capacitive loads. Figures 5–8 show the
response with capacitive loads, and the results of adding
an isolation resistor in series with the output (Figure 9).
The resistor improves the circuit’s phase margin by iso-
lating the load capacitor from the op amp’s output.
Figure 3. Rail-to-Rail Input /Output Voltage Range
Figure 4. Capacitive-Load Stability
10,000
OUT
1000
IN
100
V
A
100
CC
V
= +1
R
V
= 3V
L
OUT
TO V
= V
EE
CC
TIME (2 s/div)
/2
RESISTIVE LOAD ( )
1k
UNSTABLE
REGION
10k
100k
11

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