74LVTH162373MEA_Q Fairchild Semiconductor, 74LVTH162373MEA_Q Datasheet - Page 2

• Manufacturer Part Number: 74LVTH162373MEA_Q
• Description: Latches 16-Bit Trans Latch
• Manufacturer: Fairchild Semiconductor

Specifications of 74LVTH162373MEA_Q

• Product Category: Latches
• Rohs: yes
• Number Of Circuits: 2
• Logic Type: Transparent Latch
• Logic Family: 74LVT
• Polarity: Non-Inverting
• Number Of Output Lines: 3
• High Level Output Current: - 12 mA
• Propagation Delay Time: 5.3 ns at 2.7 V, 4.8 ns at 3.3 V
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: SSOP-48
• Mounting Style: SMD/SMT
• Number Of Input Lines: 4
• Factory Pack Quantity: 29
• Supply Current: 5 mA

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Connection Diagram
Functional Description
The LVTH162373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each
byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation.
The following description applies to each byte. When the Latch Enable (LE
latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes.
When LE
transition of LE
standard outputs are in the 2-state mode. When OE
this does not interfere with entering new data into the latches.
n
is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW
n
. The 3-STATE standard outputs are controlled by the Output Enable (OE
n
is HIGH, the standard outputs are in the high impedance mode but
2
Pin Descriptions
Truth Tables
H
L
X
Z
O
OE
LE
I
O
o
0
–I
0
LOW Voltage Level
HIGH Impedance
HIGH Voltage Level
Immaterial
Pin Names
n
–O
Previous output prior to HIGH-to-LOW transition of LE
n
15
LE
LE
H
H
X
H
H
X
L
15
L
1
2
n
) input is HIGH, data on the D
OE
OE
Inputs
Inputs
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
3-STATE Outputs
H
L
L
L
H
L
L
L
2
1
n
) input. When OE
I
I
8
Description
0
–I
X
H
X
X
H
X
L
–I
L
15
7
n
n
is LOW, the
Outputs
Outputs
O
O
enters the
8
0
O
O
–O
Z
H
–O
L
Z
H
L
o
o
15
7