74LVTH162373MTD_Q Fairchild Semiconductor, 74LVTH162373MTD_Q Datasheet - Page 5

• Manufacturer Part Number: 74LVTH162373MTD_Q
• Description: Latches 16-Bit Trans Latch
• Manufacturer: Fairchild Semiconductor

Specifications of 74LVTH162373MTD_Q

• Product Category: Latches
• Rohs: yes
• Number Of Circuits: 2
• Logic Type: Transparent Latch
• Logic Family: 74LVT
• Polarity: Non-Inverting
• Number Of Output Lines: 3
• High Level Output Current: - 12 mA
• Propagation Delay Time: 5.3 ns at 2.7 V, 4.8 ns at 3.3 V
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: TSSOP-48
• Mounting Style: SMD/SMT
• Number Of Input Lines: 4
• Factory Pack Quantity: 38
• Supply Current: 5 mA

I
'
V
V
t
t
t
t
t
t
t
t
t
t
t
t
t
C
C
CCZ
PHL
PLH
PHL
PLH
PZL
PZH
PLZ
PHZ
S
H
W
OSHL
OSLH
DC Electrical Characteristics
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than V
Dynamic Switching Characteristics
Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n
AC Electrical Characteristics
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
Capacitance
Note 10: Capacitance is measured at frequency f
I
OLP
OLV
IN
OUT
Symbol
Symbol
Symbol
CC

Symbol
Power Supply Current
Increase in Power Supply Current
(Note 6)
Quiet Output Maximum Dynamic V
Quiet Output Minimum Dynamic V
Propagation Delay
D
Propagation Delay
LE to O
Output Enable Time
Output Disable Time
Setup Time, D
Hold Time, D
LE Pulse Width
Output to Output Skew (Note 9)
n
to O
n
n
Input Capacitance
Output Capacitance
(Note 10)
n
Parameter
n
to LE
to LE
Parameter
Parameter
Parameter

1 data inputs are driven 0V to 3V. Output under test held LOW.
OL
OL
1 MHz, per MIL-STD-883, Method 3012.
V
(V)
3.3
3.3
CC
V
V
(Continued)
CC
CC
OPEN, V
3.0V, V
V
Min
(V)
3.6
3.6
CC
(Note 7)
5
O
I
Conditions
0V or V
0V or V
T
T
A
A

Min
Typ
0.8
0.8
25
OSHL

CC
40
V
CC
q
T
Min
1.3
1.4
1.7
1.4
1.6
1.0
1.6
1.8
1.0
1.0
3.0
C
CC
A
q
) or LOW-to-HIGH (t
C to

3.3V
40
Max
0.19
Max

0.2
85
q
Max
C to
r
q
C
0.3V
4.8
4.8
5.0
5.1
5.0
5.4
5.1
5.4
1.0
1.0
CC

85
or GND.
Units
Units
q
mA
C, C
mA
V
V
OSLH
L
).
Min
1.3
1.4
1.7
1.4
1.6
1.0
1.6
1.8
0.8
1.1
3.0
50pF, R
Typical
V
Outputs Disabled
One Input at V
Other Inputs at V
V
CC
4
8
CC
d
C
L
V
L
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2.7V
O
500
50 pF, R
d
Conditions
Conditions
Max
5.3
5.1
5.1
5.8
6.0
6.6
5.0
5.7
1.0
1.0
5.5V,
(Note 8)
(Note 8)
:
CC
CC

L
0.6V
or GND
Units
pF
pF
500
Units
ns
ns
ns
ns
ns
ns
ns
ns
: