74ACT299PC_Q Fairchild Semiconductor, 74ACT299PC_Q Datasheet - Page 2

• Manufacturer Part Number: 74ACT299PC_Q
• Description: Counter Shift Registers 8-Inp Shift/Stor Reg
• Manufacturer: Fairchild Semiconductor

Specifications of 74ACT299PC_Q

• Counting Sequence: Serial/Parallel to Serial/Parallel
• Number Of Circuits: 8
• Package / Case: PDIP-20
• Logic Family: 74ACT
• Logic Type: CMOS
• Number Of Input Lines: 8
• Output Type: 3-State
• Propagation Delay Time: 13.5 ns
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Function: Shift Register
• Mounting Style: Through Hole
• Number Of Output Lines: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Supply Voltage - Max: 5 V

©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
Connection Diagram
Pin Description
Functional Description
The AC/ACT299 contains eight edge-triggered D-type
flip-flops and the interstage logic necessary to perform
synchronous shift left, shift right, parallel load and hold
operations. The type of operation is determined by S
and S
are brought out through 3-STATE buffers to separate I/O
pins that also serve as data inputs in the parallel load
mode. Q
expansion in serial shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the
recommended setup and hold times, relative to the rising
edge of CP, are observed.
A HIGH signal on either OE
3-STATE buffers and puts the I/O pins in the high imped-
ance state. In this condition the shift, hold, load and reset
operations can still occur. The 3-STATE buffers are also
disabled by HIGH signals on both S
tion for a parallel load operation.
CP
DS
DS
S
MR
OE
I/O
Q
Pin Names
0
0
, S
, Q
0
7
0
1
–I/O
, OE
1
1
7
, as shown in the Truth Table. All flip-flop outputs
0
7
2
and Q
7
Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset
3-STATE Output Enable Inputs
Parallel Data Inputs or 3-STATE
Parallel Outputs
Serial Outputs
are also brought out on other pins for
Description
1
or OE
0
and S
2
disables the
1
in prepara-
0
2
Logic Symbols
Truth Table
H
L
X
MR S
H
H
H
H
L
LOW Voltage Level
Immaterial
HIGH Voltage Level
LOW-to-HIGH Transition
Inputs
X
H
H
L
L
1
S
X
H
H
L
L
0
CP
X
X
IEEE/IEC
Asynchronous Reset;
Q
Parallel Load; I/O
Shift Right;
DS
Shift Left,
DS
Hold
0
–Q
0
7
7
Q
Q
LOW
0
7
Response
, Q
, Q
0
7
n
Q
Q
www.fairchildsemi.com
1
6
, etc.
, etc.
Q
n