74LVC377D-T NXP Semiconductors, 74LVC377D-T Datasheet

no-image

74LVC377D-T

Manufacturer Part Number
74LVC377D-T
Description
Flip Flops 3.3V OCTAL POS D-TYPE ENABL
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC377D-T

Product Category
Flip Flops
Rohs
yes
Number Of Circuits
1
Logic Family
LVC
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
6 ns at 3.3 V
High Level Output Current
- 24 mA
Supply Voltage - Max
3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-163
Minimum Operating Temperature
- 40 C
Number Of Input Lines
8
Number Of Output Lines
8
Factory Pack Quantity
2000
Supply Voltage - Min
1.2 V
Part # Aliases
74LVC377D,118
1. General description
2. Features and benefits
3. Ordering information
Table 1.
Type number
74LVC377D
74LVC377DB
74LVC377PW
Ordering information
Package
Temperature
range
40 C to +125 C
40 C to +125 C
40 C to +125 C
The 74LVC377 has eight edge-triggered D-type flip-flops with individual inputs (D) and
outputs (Q). A common clock input (CP) loads all flip-flops simultaneously when data
enable input (E) is LOW. The state of each D input, one set-up time before the
LOW to HIGH clock transition, is transferred to the corresponding output (Qn) of the
flip-flop. Input E must be stable only one set-up time prior to the LOW to HIGH transition
for predictable operation.
74LVC377
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 6 — 20 November 2012
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Output drive capability 50  transmission lines at 125 C
Complies with JEDEC standard:
ESD protection:
Specified from 40 C to +85 C and from 40 C to +125 C
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Name
SO20
SSOP20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Product data sheet
Version
SOT163-1
SOT339-1
SOT360-1

Related parts for 74LVC377D-T

74LVC377D-T Summary of contents

Page 1

... Ordering information Table 1. Ordering information Type number Package Temperature range 40 C to +125 C 74LVC377D 40 C to +125 C 74LVC377DB 40 C to +125 C 74LVC377PW Name Description SO20 plastic small outline package; 20 leads; body width 7.5 mm SSOP20 plastic shrink small outline package; 20 leads; ...

Page 2

... NXP Semiconductors 4. Functional diagram Fig 1. Logic symbol 5. Pinning information 5.1 Pinning Fig 3. Pin configuration SO20 and (T)SSOP20 5.2 Pin description Table 2. Pin description Symbol Pin D[0: 13, 14, 17, 18 74LVC377_6 Product data sheet Octal D-type flip-flop with data enable ...

Page 3

... NXP Semiconductors Table 2. Pin description ?ontinued Symbol Pin Q[0: 12, 15, 16, 19 GND Functional description [1] Table 3. Function table Operating mode Control CP  Load 1  Load 0  Hold Do nothing X [ HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition ...

Page 4

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...

Page 5

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I supply current I additional per input pin; CC supply current input 3 capacitance V = GND ...

Page 6

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t hold time E to CP; see CP; see maximum see max frequency ...

Page 7

... NXP Semiconductors 11. Waveforms CP input Qn output Measurement points are given in Logic levels: V and Fig 4. Propagation delay clock (CP) to output (Qn), pulse width clock (CP), and maximum frequency CP input E input Dn input Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. ...

Page 8

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Fig 6. Test circuit for switching times Table 9. Test data Supply voltage 1 1. ...

Page 9

... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 8 ...

Page 11

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... Revision history Document ID Release date 74LVC377 v.6 20121120 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table ranges. 74LVC377 v.5 20050221 74LVC377 v ...

Page 13

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 14

... Octal D-type flip-flop with data enable; positive-edge trigger NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 15

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations ...

Related keywords