MAX9967BMCCQ+D Maxim Integrated, MAX9967BMCCQ+D Datasheet - Page 26

• Manufacturer Part Number: MAX9967BMCCQ+D
• Description: Buffers & Line Drivers
• Manufacturer: Maxim Integrated

Specifications of MAX9967BMCCQ+D

• Rohs: yes

Dual, Low-Power, 500Mbps ATE
Driver/Comparator with 35mA Load
Figure 6. Serial-Interface Timing
A CMOS-compatible serial interface controls the
MAX9967 modes (Figure 5). Control data flow into an 8-
bit shift register (MSB first) and are latched when CS is
taken high, as shown in Figure 6. Latches contain 6 con-
trol bits for each channel of the dual pin driver. Data
from the shift register are loaded to either or both of the
latches as determined by bits D6 and D7, and indicated
in Figure 5 and Table 5. The control bits, in conjunction
with external inputs DATA_ and RCV_, manage the fea-
Table 5. Shift-Register Functions
26
SCLK
DIN
BIT
D7
D6
D5
D4
D3
D2
D1
D0
CS
______________________________________________________________________________________
Serial Interface and Device Control
TMSEL
LDCAL
LLEAK
NAME
LDDIS
CH1
CH2
SC1
SC0
t
CH
t
CSS0
Channel 1 Write Enable. Set to 1 to update the control byte for channel 1. Set to 0 to make no changes to
channel 1.
Channel 2 Write Enable. Set to 1 to update the control byte for channel 2. Set to 0 to make no changes to
channel 2.
Low-Leakage Select. Set to 1 to put driver, load, and clamps into low-leakage mode. Comparators remain
active in low-leakage mode. Set to 0 for normal operation.
Driver Termination Select. Set to 1 to force the driver output to the DTV_ voltage when RCV_ = 1 (term). Set to
0 to place the driver into high-impedance mode when RCV_ = 1 (high-Z). See Table 1.
Driver Slew-Rate Select. SC1 and SC0 set the driver slew rate. See Table 2.
Load Disable. Set LDDIS to 1 to disable the load. Set to 0 for normal operation. See Table 4.
Load Calibrate. Overrides LDEN to enable load. Set LDCAL to 1 to enable load. Set LDCAL to 0 for normal
operation. See Table 4.
D7
t
DS
D6
t
OH
D5
t
CL
D4
tures of each channel, as shown in Tables 1 and 2. RST
sets LLEAK = 1 for both channels, forcing them into low-
leakage mode. All other bits are unaffected. At power-
up, hold RST low until V
Analog control input THR sets the threshold for the
input logic, allowing operation with CMOS logic as low
as 0.9V. Leaving THR unconnected results in a nominal
threshold of 1.25V from an internal reference, providing
compatibility with 2.5 to 3.3V logic.
DESCRIPTION
D3
D2
D1
CC
t
CSH1
and V
EE
D0
have stabilized.
t
CSS1
t
CSWH