MC74ACT157MEL ON Semiconductor, MC74ACT157MEL Datasheet - Page 2

• Manufacturer Part Number: MC74ACT157MEL
• Description: Encoders, Decoders, Multiplexers & Demultiplexers 5V Quad 2-Input
• Manufacturer: ON Semiconductor

Specifications of MC74ACT157MEL

• Product Category: Encoders, Decoders, Multiplexers & Demultiplexers
• Product: Multiplexers
• Logic Family: 74ACT
• Number Of Bits: 4
• Number Of Lines (input / Output): 2 / 1
• Propagation Delay Time: 7.5 ns at 5 V
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: EIAJ-16
• Minimum Operating Temperature: - 40 C
• Number Of Input Lines: 2
• Number Of Output Lines: 1
• Factory Pack Quantity: 2000

multiplexer. It selects four bits of data from two sources
under the control of a common Select input (S). The Enable
input (E) is active-LOW. When E is HIGH, all of the outputs
(Z) are forced LOW regardless of all other inputs. The
MC74AC157/74ACT157 is the logic implementation of a
4-pole, 2-position switch where the position of the switch
is determined by the logic levels supplied to the Select input.
The logic equations for the outputs are shown below:
The MC74AC157/74ACT157 is a quad 2-input
FUNCTIONAL DESCRIPTION
I
0a
Z
a
NOTE:
I
1a
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
I
0b
Z
MC74AC157, MC74ACT157
b
I
1b
S
Figure 3. Logic Diagram
Figure 2. Logic Symbol
E I
http://onsemi.com
Z
0a
a
I
I
1a
0c
I
Z
0b
b
2
Z
I
1b
c
moving of data from two groups of registers to four common
output busses. The particular register from which the data
comes is determined by the state of the Select input. A less
obvious
MC74AC157/74ACT157 can generate any four of the
sixteen different functions of two variables with one
variable common. This is useful for implementing gating
functions.
Z
I
I
1c
0c
c
Z
Z
Z
Z
A common use of the MC74AC157/74ACT157 is the
a
b
c
d
I
1c
= E
= E
= E
= E
Z
I
0d
d
•
•
•
•
(I
(I
(I
(I
I
use
I
0d
1d
1a
1c
1b
1d
•
•
•
•
S+I
S+I
S+I
S+I
Z
is
d
0a
0c
0b
0d
•
•
•
•
I
S)
S)
1d
S)
S)
as
a
E
function
S
generator.
The