MAX9123EUE-T Maxim Integrated, MAX9123EUE-T Datasheet - Page 7

• Manufacturer Part Number: MAX9123EUE-T
• Description: LVDS Interface IC
• Manufacturer: Maxim Integrated

Eliminate reflections and ensure that noise couples as
common mode by running the differential trace pairs
close together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Maintain the distance between the differential traces to
avoid discontinuities in differential impedance. Avoid
90° turns and minimize the number of vias to further
prevent impedance discontinuities.
Transmission media should have a nominal differential
impedance of 100Ω. To minimize impedance disconti-
nuities, use cables and connectors that have matched
differential impedance.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
Figure 1. Driver V
Figure 3. Driver Propagation Delay and Transition Time Waveforms
GND
V
CC
IN_
OD
and V
_______________________________________________________________________________________
OS
OUT_ -
OUT_+
V
Cables and Connectors
Test Circuit
DIFF
IN_
R
R
L
L
/2
/2
OUT_+
OUT_-
V
OS
20%
1.5V
t
PLHD
V
t
OD
TLH
0 DIFFERENTIAL
80%
0
Quad LVDS Line Driver with
V
DIFF
= (V
OUT_
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
For LVDS applications, a four-layer PC board that pro-
vides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the LVTTL/LVCMOS
and LVDS signals from each other to prevent coupling.
TRANSISTOR COUNT: 1246
PROCESS: CMOS
Figure 2. Driver Propagation Delay and Transition Time Test
Circuit
+) - (V
GENERATOR
Flow-Through Pinout
OUT_
80%
-)
1.5V
t
PHLD
t
THL
0
0
50Ω
20%
IN_
0
V
V
3V
OH
OL
Chip Information
C
C
L
L
Board Layout
R
L
OUT_ +
OUT_ -
7