MAX9163ESA Maxim Integrated, MAX9163ESA Datasheet - Page 9

• Manufacturer Part Number: MAX9163ESA
• Description: LVDS Interface IC Bus LVDS 3.3V Single Transceiver
• Manufacturer: Maxim Integrated

For example, if C
18in, and Z
impedance is:
where Z
In this example, capacitive loading reduces the charac-
teristic impedance from 120Ω to 54Ω. The load seen by
a driver located on a card in the middle of the bus is
27Ω because the driver sees two 54Ω terminations in
parallel. A typical LVDS driver (rated for a 100Ω load)
would not develop a large enough differential signal to
be detected reliably by an LVDS receiver.
The MAX9163 BLVDS driver is designed and specified
to drive a 27Ω load to differential voltage levels of
180mV to 360mV. A standard LVDS receiver is able to
detect this level of differential signal.
Short extensions off the bus, called stubs, contribute to
capacitive loading. Keep stubs less than 1in for a good
balance between ease of component placement and
good signal integrity.
The MAX9163 driver outputs are current-source drivers
and drive larger differential signal levels into resistances
higher than 27Ω and smaller levels into resistances lower
than 27Ω (see the Typical Operating Characteristics
curves). To keep loading from reducing bus impedance
below the rated 27Ω load, PC board traces can be
designed for higher unloaded characteristic impedances.
The power-on reset voltage of the MAX9163 is typically
2.2V. When the supply falls below this voltage, the
device is disabled and the outputs (DO+/RO+, DO-/RO-,
and ROUT) are high impedance.
Figure 6. Input Fail-Safe Circuit
Z
DF loaded
-
DF-loaded
DO+/RI+
DO-/RI-
DF-unloaded
=
120
Ω
O
= 54Ω
GND
V
_______________________________________________________________________________________
CC
x
= 2.5pF/in, C
[
5µA
2.5µA
2 5
35mV
.
= 120Ω, the loaded differential
pF
/ ( .
MAX9163
2 5
L
pF
Bus LVDS 3.3V Single Transceiver
= 10pF, N = 18, L =
Power-On Reset
+
(
18 10
x
ROUT
pF
/
18
in
))
]
Bypass V
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to V
In the example in the Effects of Capacitive Loading
section, the loaded differential impedance of the bus is
reduced to 54Ω. Because the bus can be driven from
any card position, it must be terminated at each end. A
parallel termination of 54Ω at each end of the bus
placed across the traces provides a proper termination.
The total load seen by the driver is 27Ω.
In a multidrop bus where the driver is at one end and
receivers are connected at regular intervals along the
bus, the bus has lowered impedance due to capacitive
loading. Assuming the same impedance as calculated
in the multidrop example (54Ω), the multidrop bus can
be terminated with a single, parallel-connected 54Ω
resistor at the far end of the driver. Only a single resis-
tor is required because the driver sees one 54Ω differ-
ential trace. The signal swings are larger with a 54Ω
load. In general, parallel terminate each end of the bus
with a resistor matching the differential impedance of
the bus (taking into account any reduced impedance
due to loading).
The characteristics of differential input and output con-
nections affect the performance of the device. Use con-
trolled-impedance traces, cables, and connectors with
matched characteristic impedance.
Ensure that noise couples as common mode by run-
ning the traces of a differential pair close together.
Reduce within-pair skew by matching the electrical
length of the conductors within a differential pair.
Excessive skew can result in a degradation of magnetic
field cancellation.
Maintain the distance between conductors within a dif-
ferential pair to avoid discontinuities in differential
impedance. Minimize the number of vias to further pre-
vent impedance discontinuities.
For BLVDS applications, a four-layer PC board with
separate power, ground, BLVDS, LVDS, and logic
signal layers is recommended. Separate the LVTTL/
LVCMOS and BLVDS signals to prevent coupling.
CC
Traces, Cables, and Connectors
with high-frequency, surface-mount
Applications Information
CC
Power-Supply Bypassing
.
Board Layout
Termination
9