74VHC16374TTR STMicroelectronics, 74VHC16374TTR Datasheet

74VHC16374TTR

Manufacturer Part Number

74VHC16374TTR

Description

Flip Flops 16-Bit "D' Flip-Flop

Manufacturer

STMicroelectronics

Datasheet

1.74VHC16374TTR.pdf (11 pages)

Specifications of 74VHC16374TTR

Product Category

Flip Flops

Rohs

yes

Number Of Circuits

Logic Family

74VHC

Logic Type

D-Type Flip-Flop

Polarity

Non-Inverting

Input Type

Single-Ended

Propagation Delay Time

16.2 ns

High Level Output Current

- 8 mA

Supply Voltage - Max

5.5 V

Maximum Operating Temperature

+ 125 C

Mounting Style

SMD/SMT

Package / Case

TSSOP-48

Minimum Operating Temperature

- 55 C

Number Of Input Lines

Number Of Output Lines

Factory Pack Quantity

2000

Supply Voltage - Min

2 V

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

74VHC16374TTR

Manufacturer:

Current page: 1 of 11
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DESCRIPTION

The 74VHC16374 is an advanced high-speed

FLIP FLOP with 3 STATE OUTPUTS NON

INVERTING fabricated with sub-micron silicon

gate and double-layer metal wiring C

technology.

These 16 bit D-TYPE flip-flop is controlled by two

clock inputs (CK) and two output enable inputs

(nOE). The device can be used as two 8-bit

flip-flops or one 16-bit flip-flop.

On the positive transition of the clock, the Q

outputs will be set to the logic state that were

setup at the D inputs.

While the (OE) input is low, the outputs will be in

a normal logic state (high or low logic level); while

OE is high, the outputs will be in a high impedance

state.

The output control does not affect the internal op-

eration of flip-flops; that is, the old data can be re-

tained or the new data can be entered even while

the outputs are off.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with protec-

tion circuits against static discharge, giving them

2KV ESD immunity and transient excess voltage.

February 2003

HIGH SPEED:

LOW POWER DISSIPATION:

HIGH NOISE IMMUNITY:

POWER DOWN PROTECTION ON INPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

BALANCED PROPAGATION DELAYS:

OPERATING VOLTAGE RANGE:

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 16374

IMPROVED LATCH-UP IMMUNITY

LOW NOISE: V

MAX

PLH

NIH

= 4 A (MAX.) at T

| = I

(OPR) = 2V to 5.5V

= 185 MHz (TYP.) at V

= V

PHL

NIL

= 8 mA (MIN)

= 28% V

OLP

= 0.9V (MAX.)

=25°C

(MIN.)

WITH 3-STATE OUTPUTS NON INVERTING

= 5V

MOS

ORDER CODES

PIN CONNECTION

PACKAGE

TSSOP

16-BIT D-TYPE FLIP FLOP

TSSOP

TUBE

74VHC16374

74VHC16374TTR

T & R

1/11

Related parts for 74VHC16374TTR

74VHC16374TTR Summary of contents

Page 1

... All inputs and outputs are equipped with protec- tion circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. February 2003 16-BIT D-TYPE FLIP FLOP = 5V CC ORDER CODES PACKAGE TSSOP PIN CONNECTION 2 MOS 74VHC16374 TSSOP TUBE T & R 74VHC16374TTR 1/11 ...

Page 2

INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1 1OE 3 State Output Enable Input (Active LOW 1Q0 to 3-State Outputs 11, 12 1Q7 13, 14, 16, 17, 2Q0 to ...

Page 3

LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage Input Diode Current ...

Page 4

DC SPECIFICATIONS Symbol Parameter V (V) V High Level Input 2.0 IH Voltage 3.0 to 5.5 V Low Level Input 2.0 IL Voltage 3.0 to 5.5 V High Level Output 2.0 OH Voltage 3.0 4.5 3.0 4.5 V Low ...

Page 5

AC ELECTRICAL CHARACTERISTICS (Input t Symbol Parameter V (V) t Propagation Delay 3.3 PLH Time t PHL 3 5.0 5.0 t Output Enable 3.3 PZL Time t PZH 3.3 5.0 5.0 t Output Disable 3.3 PLZ Time ...

Page 6

DYNAMIC SWITCHING CHARACTERISTICS Symbol Parameter V (V) V Dynamic Low OLP Voltage Quiet 5.0 V OLV Output (note 1, 2) Dynamic High V Voltage Input 5.0 IHD (note 1, 3) Dynamic Low V Voltage Input 5.0 ILD (note 1, ...

Page 7

WAVEFORM 1 PROPAGATION DELAYS, SETUP AND HOLD TIMES, MAXIMUM CLOCK FREQUENCY (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 74VHC16374 7/11 ...

Page 8

WAVEFORM 3 : CLOCK PULSE WIDTHS (f=1MHz; 50% duty cycle) 8/11 ...

Page 9

TSSOP48 MECHANICAL DATA mm. DIM. MIN 0. 0.17 c 0.09 D 12.4 E 8.1 BSC E1 6.0 e 0.5 BSC K 0˚ PIN 1 IDENTIFICATION 1 TYP MAX. MIN. 1.2 ...

Page 10

Tape & Reel TSSOP48 MECHANICAL DATA DIM. MIN 12 8.7 Bo 13.1 Ko 1.5 Po 3.9 P 11.9 10/11 mm. TYP MAX. MIN. 330 13.2 0.504 0.795 2.362 30.4 8.9 0.343 ...

Page 11

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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