72403L15SO IDT, 72403L15SO Datasheet
72403L15SO
Specifications of 72403L15SO
Related parts for 72403L15SO
72403L15SO Summary of contents
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... IN MASTER MR RESET IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES © 2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. CMOS PARALLEL FIFO has an Output Enable (OE) pin ...
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... Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested. 2. IDT72403 only. 3. Tested with outputs open ( HIGH for IDT72403. OUT 4. For frequencies greater than 10MHz 35mA + (1.5mA x [f –10MHz]) commercial, and Military availability for IDT72403 is 10MHz, 35MHz. IDT72401 is available for all MHz. Vcc ...
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... FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1μF directly between V 2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of like speed grades. 3. IDT72403 only. ...
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... FlFOs together, as shown in Figures 10 and 11. OUTPUT ENABLE (OE) (IDT72403 ONLY) Output enable is used to read FIFO data onto a bus active LOW. OUTPUTS lines DATA OUTPUT (Q Data Output lines. The IDT72401 and IDT72403 have a 4-bit data output. 4 MILITARY AND COMMERCIAL TEMPERATURE RANGES 90% 90% 10% 10% <3ns < ...
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... IDT72401/72403 CMOS PARALLEL FIFO FUNCTIONAL DESCRIPTION The FIFO is designed using a dual port RAM architecture as opposed to the traditional shift register approach. This FIFO architecture has a write pointer, a read pointer and control logic, which allow simultaneous read and write operations. The write pointer is incremented by the falling edge of the Shift In (Sl) control ...
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... IDT72401/72403 CMOS PARALLEL FIFO ( (1) INPUT DATA NOTES: 1. FIFO is initially full pulse is applied held HIGH soon as IR becomes HIGH the Input Data is loaded into the FIFO. 5. The write pointer is incremented. SI should not go LOW until (t Figure 4 ...
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... PT Figure 7. t and t Specification PT OPH t MRIRH t MRORL t MRS t MRQ Figure 8. Master Reset Timing t t HZOE OOE –500mV and V +500mV levels on the output Figure 9. Output Enable Timing, IDT72403 Only ...
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... IR will return to the LOW state until SI is brought LOW LOW when the MR is ended, IR will go HIGH, but the data in the inputs will not enter the memory until SI goes HIGH. 5. FIFOs are expandable on depth and width. However, in forming wider words, two external gates are required to generate composite Input and OR flags. This is due to the variation of delays of the FIFOs. ...
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... Commercial and Military>72401only 15 Commercial and Military 10 L Low Power 72401 FIFO 72403 FIFO for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 9 300 mil, P16-1 300 mil, D16-1 SOIC, SO16-1 Shift Frequency (fs) Speed in MHz 2747 drw 16 for Tech Support: 408-360-1753 email: FIFOhelp@idt.com ...