74ALVC16500MTD Fairchild Semiconductor, 74ALVC16500MTD Datasheet

74ALVC16500MTD

Manufacturer Part Number

74ALVC16500MTD

Description

TXRX 18BIT UNIV BUS 56TSSOP

Manufacturer

Fairchild Semiconductor

Series

74ALVCr

Datasheet

1.74ALVC16500MTD.pdf (7 pages)

Specifications of 74ALVC16500MTD

Logic Type

Universal Bus Transceiver

Number Of Circuits

18-Bit

Current - Output High, Low

24mA, 24mA

Voltage - Supply

1.65 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74ALVC16500MTD

74ALVC16500

Low Voltage 18-Bit Universal Bus Transceivers

with 3.6V Tolerant Inputs and Outputs

General Description

The ALVC16500 is an 18-bit universal bus transceiver

which combines D-type latches and D-type flip-flops to

allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the

device operates in the transparent mode when LEAB is

HIGH. When LEAB is LOW, the A data is latched if CLKAB

is held at a HIGH or LOW logic level. If LEAB is LOW, the A

bus data is stored in the latch/flip-flop on the HIGH-to-LOW

transition of CLKAB. When OEAB is HIGH, the outputs are

active. When OEAB is LOW, the outputs are in a high-

impedance state.

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, and CLKBA. The output enables are com-

plementary (OEAB is active HIGH and OEBA is active

LOW).

The ALVC16500 is designed for low voltage (1.65V to

3.6V) V

The 74ALVC16500 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

applications with I/O capability up to 3.6V.

Package Number

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500684

Features

Note 1: To ensure the high-impedance state during power up or power

down, OEBA should be tied to V

should be tied to GND through a pull-down resistors; the minimum value of

the resistor is determined by the current-sourcing capability of the driver.

1.65V–3.6V V

3.6V tolerant inputs and outputs

Power-off high impedance inputs and outputs

Supports live insertion/withdrawal (Note 1)

Uses patented noise/EMI reduction circuitry

Latchup conforms to JEDEC JED78

ESD performance:

3.4 ns max for 3.0V to 3.6V V

4.0 ns max for 2.3V to 2.7V V

7.0 ns max for 1.65V to 1.95V V

Human body model

Machine model 200V

(A to B, B to A)

Package Description

supply operation

2000V

through a pull-up resistor and OEAB

October 2001

Revised October 2001

www.fairchildsemi.com

Related parts for 74ALVC16500MTD

74ALVC16500MTD Summary of contents

Page 1

... CMOS power dissipation. Ordering Code: Order Number Package Number 74ALVC16500MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation Features 1.65V– ...

Page 2

Connection Diagram www.fairchildsemi.com Pin Descriptions Pin Names Description OEAB Output Enable Input for Direction (Active HIGH) OEBA Output Enable Input for Direction (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, Clock Inputs CLKBA A ...

Page 3

Logic Diagram 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 6) 0. Input Diode Current ( Output Diode Current (I ) ...

Page 5

AC Electrical Characteristics Symbol Parameter V CC Min f Maximum Clock Frequency 250 MAX Propagation Delay PHL PLH 1.1 Bus to Bus Propagation Delay PHL PLH 1.1 Clock to Bus Propagation ...

Page 6

AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3. FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 4. 3-STATE Output ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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