74ALVC16500MTD Fairchild Semiconductor, 74ALVC16500MTD Datasheet
74ALVC16500MTD
Specifications of 74ALVC16500MTD
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74ALVC16500MTD Summary of contents
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... CMOS power dissipation. Ordering Code: Order Number Package Number 74ALVC16500MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation Features 1.65V– ...
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Connection Diagram www.fairchildsemi.com Pin Descriptions Pin Names Description OEAB Output Enable Input for Direction (Active HIGH) OEBA Output Enable Input for Direction (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, Clock Inputs CLKBA A ...
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Logic Diagram 3 www.fairchildsemi.com ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 6) 0. Input Diode Current ( Output Diode Current (I ) ...
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AC Electrical Characteristics Symbol Parameter V CC Min f Maximum Clock Frequency 250 MAX Propagation Delay PHL PLH 1.1 Bus to Bus Propagation Delay PHL PLH 1.1 Clock to Bus Propagation ...
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AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3. FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 4. 3-STATE Output ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...