74VCX16835MTDX Fairchild Semiconductor, 74VCX16835MTDX Datasheet

74VCX16835MTDX

Manufacturer Part Number

74VCX16835MTDX

Description

IC UNIV BUS DVR 18BIT 56TSSOP

Manufacturer

Fairchild Semiconductor

Series

74VCXr

Datasheet

1.74VCX16835MTDX.pdf (10 pages)

Specifications of 74VCX16835MTDX

Logic Type

Universal Bus Driver, CMOS

Number Of Circuits

18-Bit

Current - Output High, Low

24mA, 24mA

Voltage - Supply

1.65 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74VCX16835GX

(Note 2)

74VCX16835MTD

(Note 3)

74VCX16835

Low Voltage 18-Bit Universal Bus Driver

with 3.6V Tolerant Inputs and Outputs

General Description

The VCX16835 low voltage 18-bit universal bus driver

combines D-type latches and D-type flip-flops to allow data

flow in transparent, latched and clocked modes.

Data flow is controlled by output-enable (OE), latch-enable

(LE), and clock (CLK) inputs. The device operates in

Transparent Mode when LE is held HIGH. The device

operates in clocked mode when LE is LOW and CLK is tog-

gled. Data transfers from the Inputs (I

Positive Edge Transition of the Clock. When OE is LOW,

the output data is enabled. When OE is HIGH the output

port is in a high impedance state.

The 74VCX16835 is designed for low voltage (1.65V to

3.6V) V

The 74VCX16835 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Note 2: BGA package available in Tape and Reel only.

Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

applications with I/O capability up to 3.6V.

Package Number

(Preliminary)

BGA54A

MTD56

) to Ouputs (O

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500173

) on a

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

the minimum value of the resistor is determined by the current sourcing

capability of the driver.

Compatible with PC100 DIMM module specifications

1.65V–3.6V V

3.6V tolerant inputs and outputs

Power-down high impedance inputs and outputs

Supports live insertion/withdrawal (Note 1)

Static Drive (I

Latchup performance exceeds 300 mA

ESD performance:

Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

4.2ns max for 3.0V to 3.6V V

5.2ns max for 2.3V to 2.7V V

9.2ns max for 1.65V to 1.95V V

Human body model

Machine model 200V

24mA @ 3.0V

18mA @ 2.3V

6mA @ 1.65V

(CLK to O

Package Description

)

supply operation

)

(OE to GND) through a pulldown resistor;

2000V

October 1998

Revised August 2001

www.fairchildsemi.com

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74VCX16835MTDX Summary of contents

Page 1

... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 3) Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation Features Compatible with PC100 DIMM module specifications 1.65V–3.6V V ...

Page 2

Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) LE Latch Enable Input CLK Clock Input Data Inputs ...

Page 3

Logic Diagram 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 7) 0 Input Diode Current ( Output ...

Page 5

DC Electrical Characteristics (2.3V Symbol Parameter V HIGH Level Input Voltage IH V LOW Level Input Voltage IL V HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ ...

Page 6

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t , Propagation Delay PHL t Bus to Bus PLH t , Propagation Delay PHL t Clock to Bus PLH t , Propagation Delay PHL Bus PLH ...

Page 7

Capacitance Symbol Parameter C Input Capacitance IN C Input/Output Capacitance I/O C Power Dissipation Capacitance Characteristics OUT OUT FIGURE 1. Characteristics for Output - Pull Up Driver FIGURE 2. Characteristics for Output - Pull Down Driver ...

Page 8

AC Loading and Waveforms TEST PLH PHL PZL PLZ PZH PHZ FIGURE 4. Waveform for Inverting and Non-inverting Functions t t 2.0ns, 10 FIGURE 6. 3-STATE Output ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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