72V251L15J IDT, 72V251L15J Datasheet
72V251L15J
Specifications of 72V251L15J
Related parts for 72V251L15J
72V251L15J Summary of contents
Page 1
... WRITE POINTER RESET LOGIC RS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ©2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...
Page 2
... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 PIN CONFIGURATION INDEX PAF 3 PAE 4 5 GND REN1 6 7 RCLK REN2 TQFP (PR32-1, order code: PF) ...
Page 3
... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating (2) V Terminal Voltage with TERM Respect to GND T Storage Temperature STG I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
Page 4
... Skew time between Read Clock & Write SKEW2 Clock for Almost-Empty Flag & Almost-Full Flag NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Industrial temperature range is available by special order for speed grades faster than 15ns. 3. Values guaranteed by design, not currently tested. AC TEST CONDITIONS In Pulse Levels ...
Page 5
... Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full. The FIFO is configured to have programmable flags when the Write Enable 2/Load (WEN2/LD) is set LOW at Reset (RS = LOW). The IDT72V201/72V211/ 72V221/72V231/72V241/72V251 devices contain four 8-bit offset registers which can be loaded with data on the inputs, or read on the outputs. See Figure 3 for details of the size of the registers and the default values ...
Page 6
... Full Offset (LSB) Default Value 007H (MSB) 0000 COMMERCIAL AND INDUSTRIAL 6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V221 - 1,024 x 9-BIT Empty Offset (LSB) Reg. Default Value 007H 8 0 (MSB Full Offset (LSB) Reg. Default Value 007H ...
Page 7
... The Full Flag (FF) will go LOW, inhibiting further write operation, when the device is full reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 256 writes for the IDT72V201, 512 writes for the IDT72V211, 1,024 writes for the IDT72V221, 2,048 writes for the IDT72V231, 4,096 writes for the IDT72V241 and 8,192 writes for the IDT72V251 ...
Page 8
... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 REN1, REN2 WEN1 (1) WEN2/LD EF, PAE FF, PAF NOTES: 1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers ...
Page 9
... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 CLKH RCLK t t ENS ENH REN1, REN2 OLZ OE WCLK WEN1 WEN2 NOTE: is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between 1 ...
Page 10
... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 WRITE WCLK t SKEW1 WEN1 WEN2 (If Applicable) RCLK t ENH t ENS REN1, REN2 OE LOW DATA IN OUTPUT REGISTER 0 8 NOTE: 1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO. ...
Page 11
... NOTES PAF offset. 2. 256 - m words in FIFO for IDT72V201, 512 - m words for IDT72V211, 1,024 - m words for IDT72V221, 2,048 - m words for IDT72V231, 4,096 - m words for IDT72V241, 8,192 - m words for IDT72V251. is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and 3 ...
Page 12
... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 CLK t t CLKH CLKL WCLK t ENS LD t ENS WEN1 PAE OFFSET (LSB) t CLK t t CLKH CLKL RCLK t ENS LD t ENS REN1, ...
Page 13
... Figure 14. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 Synchronous FIFO WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting the corresponding input controls signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF) ...
Page 14
... SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 14 Clock Cycle Time (t ) CLK Speed in Nanoseconds ⎯ 3.3V SyncFIFO™ ⎯ 3.3V SyncFIFO™ ⎯ 3.3V SyncFIFO™ ⎯ 3.3V SyncFIFO™ ⎯ 3.3V SyncFIFO™ ⎯ 3.3V SyncFIFO™ 4092 drw 18 for Tech Support: 408-360-1753 email: FIFOhelp@idt.com ...