72V2101L15PFI IDT, 72V2101L15PFI Datasheet - Page 15

• Manufacturer Part Number: 72V2101L15PFI
• Description: FIFO 256Kx9 SUPERSYNC FIFO, 3.3V
• Manufacturer: IDT

Specifications of 72V2101L15PFI

• Part # Aliases: IDT72V2101L15PFI

mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are written
to the FIFO. The PAF will go LOW after (262,144-m) writes for the IDT72V2101
and (524,288-m) writes for the IDT72V2111. The offset “m” is the full offset
value. The default setting for this value is stated in the footnote of Table 1.
IDT72V2101 and (524,289-m) writes for the IDT72V2111, where m is the
full offset value. The default setting for this value is stated in the footnote
of Table 2.
FWFT Mode), for the relevant timing information.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
In IDT Standard mode, EF is a double register-buffered output. In FWFT
In FWFT mode, the PAF will go LOW after (262,145-m) writes for the
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard and
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
PAF is synchronous and updated on the rising edge of WCLK.
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
EF/OR is synchronous and updated on the rising edge of RCLK.
TM
262,144 x 9, 524,288 x 9
15
in the FIFO. The default setting for this value is stated in the footnote of Table 2.
and FWFT Mode), for the relevant timing information.
HALF-FULL FLAG (HF)
beyond half-full sets HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 262,144
for the IDT72V2101 and 524,288 for the IDT72V2111.
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 262,145 for the
IDT72V2101 and 524,289 for the IDT72V2111.
for the relevant timing information. Because HF is updated by both RCLK
and WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Standard
In FWFT mode, the PAE will go LOW when there are n+1 words or less
PAE is synchronous and updated on the rising edge of RCLK.
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
In IDT Standard mode, if no reads are performed after reset (MRS or
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(Q
0
- Q
8
) are data outputs for 9-bit wide data.
0
-Q
8
)
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TEMPERATURE RANGES