72V275L15TFI IDT, 72V275L15TFI Datasheet - Page 19

• Manufacturer Part Number: 72V275L15TFI
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V275L15TFI

• Part # Aliases: IDT72V275L15TFI

Q
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure. D = 32,768
5. EF goes HIGH at 60ns + 1 RCLK cycle + t
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
WCLK
0
RCLK
for IDT72V275 and 65,536 for IDT72V285.
WEN
REN
- Q
PAE
PAF
1
HF
= first word written to the FIFO after Master Reset, W
EF
RT
n
t
ENS
W
x
t
t
A
ENH
t
ENS
t
RTS
REF
t
RTS
.
Figure 11. Retransmit Timing (IDT Standard Mode)
2
= second word written to the FIFO after Master Reset.
TM
t
t
t
ENH
REF
HF
t
SKEW2
1
W
x+1
19
2
t
PAF
1
t
ENS
2
t
t
t
A
REF
PAE
COMMERCIAL AND INDUSTRIAL
(5)
W
TEMPERATURE RANGES
1
(3)
t
t
ENH
A
4512 drw 14
W
2
(3)