72V285L10PF IDT, 72V285L10PF Datasheet - Page 16
![no-image](/images/no-image-200.jpg)
72V285L10PF
Manufacturer Part Number
72V285L10PF
Description
FIFO
Manufacturer
IDT
Datasheet
1.72V285L10PFG.pdf
(25 pages)
Specifications of 72V285L10PF
Part # Aliases
IDT72V285L10PF
NOTES:
1. t
2. LD = HIGH.
3. First word latency: 60ns + t
NOTES:
1. t
2. LD = HIGH, OE = LOW, EF = HIGH.
Q
Q
D
D
WCLK
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
RCLK
0
0
WCLK
0
0
WEN
RCLK
of WCLK and the rising edge of RCLK is less than t
REN
edge of the RCLK and the rising edge of the WCLK is less than t
- Q
- D
SKEW3
WEN
SKEW1
REN
- D
- Q
OE
EF
n
FF
n
n
n
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t
t
ENS
t
DATA IN OUTPUT REGISTER
ENS
t
t
OLZ
t
SKEW1
ENH
t
REF
t
A
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
t
OE
REF
(1)
+ 1*T
t
SKEW3
t
t
ENH
ENS
t
DS
RCLK
t
A
D
(1)
1
0
.
NO WRITE
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
NO OPERATION
t
t
DHS
ENH
SKEW3
LAST WORD
1
, then EF deassertion may be delayed one extra RCLK cycle.
TM
2
t
SKEW1
WFF
, then the FF deassertion may be delayed one extra WCLK cycle.
t
t
OHZ
t
DS
t
DS
ENS
t
CLKH
D
D
1
NO OPERATION
X
t
WFF
t
t
ENH
DH
DATA READ
16
t
t
DH
CLK
2
t
CLKL
t
CLKH
t
t
REF
ENS
t
OLZ
t
SKEW1
t
CLK
(1)
t
CLKL
t
ENS
t
ENH
LAST WORD
t
A
1
NO WRITE
t
ENH
t
A
COMMERCIAL AND INDUSTRIAL
WFF
REF
2
). If the time between the rising edge
). If the time between the rising
TEMPERATURE RANGES
NEXT DATA READ
t
t
ENS
WFF
t
DS
D
0
D
X
+1
t
REF
t
t
ENH
A
4512 drw 10
t
DH
t
WFF
4512 drw 11
D
1