72V851L10PF IDT, 72V851L10PF Datasheet - Page 9

• Manufacturer Part Number: 72V851L10PF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V851L10PF

• Part # Aliases: IDT72V851L10PF

NOTES:
1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second Write Enable pin. Holding WENA2/LDA (WENB2/LDB) LOW during reset will make
2. After reset, QA
3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
NOTE:
1. t
WCLKA (WCLKB)
WENA2 (WENB2)
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
(RENB1, RENB2)
(RENB1, RENB2)
RCLKA (RCLKB)
RENA1, RENA2
RENA1, RENA2
the pin act as a load enable for the programmable flag offset registers.
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than t
edge.
SKEW1
(WENB2/LDB)
(If Applicable)
WENA2/LDA
(EFB, PAEB)
(FFA, PAFA)
EFA, PAEA
(QB
FFA, PAFA
RSA (RSB)
(DA
QA
DB
is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time
(WENB1)
(WENB1)
WENA1
0
WENA1
0
0
0
- QB
- QA
- DB
(FFB)
- DA
0
FFA
- QA
8
8
8
)
8
)
(1)
8
(QB
t
SKEW1 (1)
0
- QB
8
) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.
t
CLKH
t
t
t
t
WFF
RSF
RSF
RSF
t
DATA IN VALID
RS
Figure 5. Write Cycle Timing
Figure 4. Reset Timing
t
t
t
RSS
RSS
RSS
t
CLK
9
t
CLKL
t
t
ENS
ENS
t
DS
SKEW1
TM
, then FFA (FFB) may not change state until the next WCLKA (WCLKB)
t
t
t
t
t
t
ENH
RSR
RSR
RSR
DH
ENH
t
WFF
OEA (OEB) = 1
OEA (OEB) = 0
NO OPERATION
NO OPERATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
(2)
OCTOBER 22, 2008
4093 drw 06
4093 drw 07