DS26528GNA4 Maxim Integrated, DS26528GNA4 Datasheet - Page 224
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DS26528GNA4
Manufacturer Part Number
DS26528GNA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26528GNA4.pdf
(276 pages)
Specifications of DS26528GNA4
Part # Aliases
90-26528-NA4
- Current page: 224 of 276
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 4: Receiver Signal Level 3 to 0 (RSL[3:0]). Real-time receive signal level as shown in
that the range of signal levels reported the RSL[3:0] is limited by the Equalizer Gain Limit (EGL) in short-haul
applications.
Table 9-17. Receive Level Indication
RSL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RSL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RSL3
7
0
RSL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LRSL
LIU Receive Signal Level Register
1006h + (20h x n): where n = 0 to 7, for Ports 1 to 8
RSL2
6
0
RSL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RLS1
5
0
-10 to -12.5
-12.5 to -15
-15 to -17.5
-17.5 to -20
-7.5 to -10
-20 to -23
-23 to -26
-26 to -29
-29 to -32
-32 to -36
-2.5 to -5
-5 to -7.5
> -2.5
< -36
T1
—
—
RECEIVE LEVEL (dB)
224 of 276
RLS0
4
0
-10 to -12.5
-12.5 to -15
-15 to -17.5
-17.5 to -20
-7.5 to -10
-20 to -23
-23 to -26
-26 to -29
-29 to -32
-32 to -36
-36 to -40
-40 to -44
-2.5 to -5
-5 to -7.5
—
> -2.5
< -44
3
0
E1
DS26528 Octal T1/E1/J1 Transceiver
—
2
0
—
1
0
Table
9-17. Note
—
0
0
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