DS2155GB/T&R Maxim Integrated, DS2155GB/T&R Datasheet - Page 131
DS2155GB/T&R
Manufacturer Part Number
DS2155GB/T&R
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS2155GNB.pdf
(238 pages)
Specifications of DS2155GB/T&R
Part # Aliases
90-2155G-BTR
- Current page: 131 of 238
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23.3 HDLC Mapping
23.3.1 Receive
The HDLC controllers must be assigned a space in the T1/E1 bandwidth in which they transmit and
receive data. The controllers can be mapped to either the FDL (T1), Sa bits (E1), or to channels. If
mapped to channels, then any channel or combination of channels, contiguous or not, can be assigned to
an HDLC controller. When assigned to a channel(s), any combination of bits within the channel(s) can be
avoided.
The HxRCS1–HxRCS4 registers are used to assign the receive controllers to channels 1–24 (T1) or
1–32 (E1) according to the following table:
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive HDLC Channel Select Bit 0 (RHCS0). Select Channel 1, 9, 17, or 25.
Bit 1/Receive HDLC Channel Select Bit 1 (RHCS1). Select Channel 2, 10, 18, or 26.
Bit 2/Receive HDLC Channel Select Bit 2 (RHCS2). Select Channel 3, 11, 19, or 27.
Bit 3/Receive HDLC Channel Select Bit 3 (RHCS3). Select Channel 4, 12, 20, or 28.
Bit 4/Receive HDLC Channel Select Bit 4 (RHCS4). Select Channel 5, 13, 21, or 29.
Bit 5/Receive HDLC Channel Select Bit 5 (RHCS5). Select Channel 6, 14, 22, or 30.
Bit 6/Receive HDLC Channel Select Bit 6 (RHCS6). Select Channel 7, 15, 23, or 31.
Bit 7/Receive HDLC Channel Select Bit 7 (RHCS7). Select Channel 8, 16, 24, or 32.
HxRCS1
HxRCS2
HxRCS3
HxRCS4
Register
RHCS7
7
0
RHCS6
H1RCS1, H1RCS2, H1RCS3, H1RCS4
H2RCS1, H2RCS2, H2RCS3, H2RCS4
HDLC # 1 Receive Channel Select x
HDLC # 2 Receive Channel Select x
92h, 93h, 94h, 95h
A2h, A3h, A4h, A5h
6
0
Channels
17–24
25–32
9–16
1–8
RHCS5
5
0
RHCS4
4
0
131 of 238
RHCS3
3
0
RHCS2
2
0
RHCS1
1
0
RHCS0
0
0
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