DS32512NW Maxim Integrated, DS32512NW Datasheet - Page 45

• Manufacturer Part Number: DS32512NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512NW

• Part # Aliases: 90-32512-NW0

continues to transmit, the DS325xx continues to write the data received and increment its address counter. After
the address counter reaches 7FFh it rolls over to address 000h and continues to increment.
Burst Reads. See
The DS325xx then responds with the requested data byte on SDO, increments its address counter, and prefetches
the next data byte. If the bus master continues to demand data, the DS325xx continues to provide the data on
SDO, increment its address counter, and prefetch the following byte. After the address counter reaches 7FFh it
rolls over to address 000h and continues to increment.
Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by
pulling
of the next transaction. If a write transaction is terminated prior to the
byte, the current data byte is not written.
Design Option: Wiring SDI and SDO Together. Because communication between the bus master and the
DS325xx is half-duplex, the
this option, the bus master must not drive the
AC Timing. See
Figure 8-10. SPI Clock Polarity and Phase Options
CS
high. In response to early terminations, the DS325xx resets its SPI interface logic and waits for the start
SDI/SDO
SCK
SCK
SCK
SCK
CS
Table 11-9
Figure
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
8-11. After
and
SDI
Figure 11-11
and
MSB
CS
SDO
CLOCK EDGE USED FOR DATA CAPTURE (ALL MODES)
goes low, the bus master transmits a read control word with BURST = 1.
pins can be wired together externally to reduce wire count. To support
6
SDI/SDO
for AC timing specifications for the SPI interface.
5
45 of 130
line when the DS325xx is transmitting.
4
3
SCLK
2
edge that latches the LSB of a data
DS32506/DS32508/DS32512
1
LSB