DS32508N-W Maxim Integrated, DS32508N-W Datasheet - Page 103
![no-image](/images/no-image-200.jpg)
DS32508N-W
Manufacturer Part Number
DS32508N-W
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS32512W.pdf
(130 pages)
Specifications of DS32508N-W
Part # Aliases
90-32508-NW0
- Current page: 103 of 130
- Download datasheet (2Mb)
Table 11-9. SPI Interface Timing
(VDD18 = 1.8V ±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, T
(See
Note 1:
SCLK Frequency
SCLK Cycle Time
CS
CS
SCLK High Time
SCLK Low Time
SDI Data Setup Time
SDI Data Hold Time
SDO Enable Time (High Impedance to Output Active)
SDO Disable Time (Output Active to High Impedance)
SDO Data Valid Time
SDO Data Hold Time After Update SCLK Edge
Setup to First SCLK Edge
Hold Time After Last SCLK Edge
Figure
All timing is specified with 100 pF load on all SPI pins.
11-11.) (Note 1)
PARAMETER
103 of 130
SYMBOL
A
t
t
f
t
t
t
t
CLKH
t
t
t
CLKL
= -40°C to +85°C.)
HDC
t
t
HDO
BUS
CYC
SUC
SUI
HDI
DIS
EN
DV
MIN
100
15
15
50
50
15
5
0
5
DS32506/DS32508/DS32512
TYP
MAX
10
25
40
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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