72V2105L10PF IDT, 72V2105L10PF Datasheet - Page 24

• Manufacturer Part Number: 72V2105L10PF
• Description: FIFO 256Kx18 3.3V SUPERSYNC FIFO
• Manufacturer: IDT

Specifications of 72V2105L10PF

• Part # Aliases: IDT72V2105L10PF

OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR
assertion to vary by one cycle between FIFOs. In IDT Standard mode, such
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
Word width may be increased simply by connecting together the control
GATE
FIRST WORD FALL THROUGH/
(1)
DATA IN
SERIAL INPUT (FWFT/SI)
FULL FLAG/INPUT READY (FF/IR) #2
MASTER RESET (MRS)
FULL FLAG/INPUT READY (FF/IR) #1
PARTIAL RESET (PRS)
RETRANSMIT (RT)
TM
131,072 x 18, 262,144 x 18
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
Figure 19. Block Diagram of 131,072 x 36 and 262,144 x 36 Width Expansion
D
0
-
LOAD (LD)
Dm
m
72V2105
72V295
FIFO
IDT
#1
Dm
m
+1
- Dn
Q
24
n
0
-
problems can be avoided by creating composite flags, that is, ANDing EF
of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
composite flags can be created by ORing OR of every FIFO, and separately
ORing IR of every FIFO.
72V2105 devices. D
and Q
can be attained by adding additional IDT72V295/72V2105 devices.
Qm
Figure 23 demonstrates a width expansion using two IDT72V295/
72V2105
72V295
0
FIFO
IDT
-Q
#2
17
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
from each device form a 36-bit wide output bus. Any word width
n
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
E
MPTY FLAG/OUTPUT READY (EF/OR) #2
Qm
0
-D
+1
17
- Qn
from each device form a 36-bit wide input bus
m + n
DATA OUT
4668 drw 22
GATE
(1)