MM74HC273N_Q Fairchild Semiconductor, MM74HC273N_Q Datasheet

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MM74HC273N_Q

Manufacturer Part Number
MM74HC273N_Q
Description
Flip Flops Oct D-Type Flip-Flop
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of MM74HC273N_Q

Product Category
Flip Flops
Number Of Circuits
8
Logic Family
74HC
Logic Type
D-Type Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
135 ns
High Level Output Current
- 5.2 mA
Supply Voltage - Max
6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-20
Minimum Operating Temperature
- 40 C
Number Of Input Lines
8
Number Of Output Lines
8
Supply Voltage - Min
2 V
© 2005 Fairchild Semiconductor Corporation
MM74HC273WM
MM74HC273SJ
MM74HC273MTC
MM74HC273N
MM74HC273
Octal D-Type Flip-Flops with Clear
General Description
The MM74HC273 edge triggered flip-flops utilize advanced
silicon-gate CMOS technology to implement D-type flip-
flops. They possess high noise immunity, low power, and
speeds comparable to low power Schottky TTL circuits.
This device contains 8 master-slave flip-flops with a com-
mon clock and common clear. Data on the D input having
the specified setup and hold times is transferred to the Q
output on the LOW-to-HIGH transition of the CLOCK input.
The CLEAR input when LOW, sets all outputs to a low
state.
Each output can drive 10 low power Schottky TTL equiva-
lent loads. The MM74HC273 is functionally as well as pin
compatible to the 74LS273. All inputs are protected from
damage due to static discharge by diodes to V
ground.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
MTC20
M20D
M20B
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DS005331
CC
and
Top View
Features
Typical propagation delay: 18 ns
Wide operating voltage range
Low input current: 1
Low quiescent current: 80
Output drive: 10 LS-TTL loads
Package Description
P
A maximum
P
A (74 Series)
September 1983
Revised May 2005
www.fairchildsemi.com

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MM74HC273N_Q Summary of contents

Page 1

... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2005 Fairchild Semiconductor Corporation Features Typical propagation delay Wide operating voltage range ...

Page 2

Truth Table (Each Flip-Flop) Inputs Clear Clock HIGH Level (Steady State) L LOW Level (Steady State) X Don’t Care n Transition from LOW-to-HIGH level Q The ...

Page 3

Absolute Maximum Ratings (Note 2) Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Clamp Diode Current ( Output Current, per pin (I ) ...

Page 4

AC Electrical Characteristics Symbol Parameter f Maximum Operating Frequency MAX Maximum Propagation PHL PLH Delay, Clock to Output t ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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