93LC56B/P Microchip Technology, 93LC56B/P Datasheet - Page 11
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93LC56B/P
Manufacturer Part Number
93LC56B/P
Description
IC EEPROM 2KBIT 3MHZ 8DIP
Manufacturer
Microchip Technology
Specifications of 93LC56B/P
Memory Size
2K (128 x 16)
Package / Case
8-DIP (0.300", 7.62mm)
Operating Temperature
0°C ~ 70°C
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
2MHz, 3MHz
Interface
Microwire, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Organization
128 K x 16
Interface Type
Microwire
Maximum Clock Frequency
2 MHz
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
0.5 mA
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Operating Supply Voltage
2.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
93LC56B/PR
93LC56B/PR
93LC56B/PR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
93LC56B/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
2.9
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA56A/B/C and 93LC56A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C56A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction,
but the chip must be in the EWEN status.
FIGURE 2-10:
FIGURE 2-11:
© 2008 Microchip Technology Inc.
CLK
CLK
DO
DO
CS
CS
V
DI
DI
CC
must be ≥4.5V for proper operation of WRAL.
Write All (WRAL)
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
1
1
High-Z
High-Z
WRAL TIMING FOR 93AA AND 93LC DEVICES
WRAL TIMING FOR 93C DEVICES
0
0
0
0
0
0
1
1
x
x
•••
•••
x
x
The DO pin indicates the Ready/
device if CS is brought high after a minimum of 250 ns
low (T
V
Dx
Dx
CC
Note:
must be ≥4.5V for proper operation of WRAL.
CSL
•••
•••
).
D0
D0
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/
T
T
CSL
CSL
T
WL
T
WL
Busy
Busy
T
T
SV
SV
Ready
Ready
Busy
Busy
H
H
DS21794F-page 11
status from DO.
IGH
IGH
T
T
-Z
status of the
-Z
CZ
CZ