72V265LA15PF IDT, 72V265LA15PF Datasheet - Page 20

• Manufacturer Part Number: 72V265LA15PF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V265LA15PF

• Part # Aliases: IDT72V265LA15PF

NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W
4. No more than D –2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
5. EF goes HIGH at 60 ns + 1 RCLK cycle + t
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
Q
D = 8,192 for IDT72V255LA and 16,384 for IDT72V265LA.
WCLK
1
RCLK
0
WEN
= first word written to the FIFO after Master Reset, W
REN
PAE
PAF
- Q
RT
HF
EF
n
t
ENS
W
x
t
t
A
ENH
t
ENS
t
REF
RTS
.
t
RTS
Figure 11. Retransmit Timing (IDT Standard Mode)
2
= second word written to the FIFO after Master Reset.
t
t
t
ENH
REF
HF
t
SKEW4
1
W
x+1
20
2
t
PAF
1
t
ENS
2
t
COMMERCIAL AND INDUSTRIAL
t
t
A
REF
PAE
(5)
TEMPERATURE RANGES
W
1
(3)
OCTOBER 22, 2008
t
t
A
ENH
4672 drw14
W
2
(3)