24AA014H-I/SN Microchip Technology, 24AA014H-I/SN Datasheet - Page 5

• Manufacturer Part Number: 24AA014H-I/SN
• Description: IC EEPROM 1KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24AA014H-I/SN

• Memory Size: 1K (128 x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Organization: 128 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.7 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.8 V , 2.5 V , 3.3 V , 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2.0
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
2.1
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to V
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
The SCL input is used to synchronize the data transfer
to and from the device.
2.3
The A0, A1 and A2 inputs are used by the 24AA014H/
24LC014H for multiple device operations. The levels
on these inputs are compared with the corresponding
bits in the slave address. The chip is selected if the
compare is true.
Up to eight 24AA014H/24LC014H devices may be
connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either V
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
© 2008 Microchip Technology Inc.
A0
A1
A2
V
SDA
SCL
WP
V
SS
CC
Name
PIN DESCRIPTIONS
SDA Serial Data
SCL Serial Clock
A0, A1, A2
CC
8-pin
PDIP
(typical 10 kΩ for 100 kHz, 2 kΩ for
1
2
3
4
5
6
7
8
PIN FUNCTION TABLE
CC
or V
SOIC
SS
8-pin
1
2
3
4
5
6
7
8
.
TSSOP
8-pin
1
2
3
4
5
6
7
8
Preliminary
MSOP
8-pin
1
2
3
4
5
6
7
8
24AA014H/24LC014H
2.4
WP is the hardware write-protect pin. It must be tied to
V
is enabled and will protect half of the array (40h-7Fh).
If the WP pin is tied to V
protection is disabled.
2.5
The 24AA014H/24LC014H employs a V
detector circuit that disables the internal erase/write
logic if the V
The SCL and SDA inputs have Schmitt Trigger and
filter circuits that suppress noise spikes to assure
proper device operation even on a noisy bus.
CC
or V
TDFN
8-pin
1
2
3
4
5
6
7
8
SS
WP
Noise Protection
. If tied to V
CC
is below 1.5 volts at nominal conditions.
User Configurable Chip Select
User Configurable Chip Select
User Configurable Chip Select
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.7V to 5.5V (24AA014H)
+2.5V to 5.5V (24LC014H)
CC
, the hardware write protection
Function
SS
the hardware write
DS22077B-page 5
CC
threshold