72V851L20TF8 IDT, 72V851L20TF8 Datasheet - Page 11

• Manufacturer Part Number: 72V851L20TF8
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V851L20TF8

• Part # Aliases: IDT72V851L20TF8

NOTE:
1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
NOTE:
1. When t
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
WENA1, (WENB1)
(If Applicable)
WCLKA (WCLKB)
WENA2 (WENB2)
When
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
(RENB1, RENB2)
(DB
RCLKA (RLCKB)
(QB
RENA1, RENA2
FFA (FFB)
DA
QA
(WCLKB)
(WENB2)
(WENB1)
(RCLKB)
(RENB2)
0
(If Applicable)
WCLKA
WENA2
WENA1
0
RCLKA
RENA1
t
0
SKEW1
SKEW1
- DB
0
(OEB)
(QB
- QB
(DB
OEA (OEB)
- DA
- QA
EFA (EFB)
OEA
QA
DA
8
0
0
8
8
≥ minimum specification, t
< minimum specification, t
0
0
)
8
)
- QB
- DB
- QA
- DA
LOW
8
8
8
8
)
)
DATA IN OUTPUT REGISTER
t
t
ENS
t
LOW
DS
ENS
t
ENS
t
NO WRITE
SKEW1
DATA WRITE 1
FRL
FRL
DATA IN OUTPUT REGISTER
t
maximum = 2t
maximum = t
SKEW1
t
t
t
ENH
ENH
ENH
t
A
CLK
t
WFF
CLK
t
FRL
+ t
+ t
t
REF
SKEW1
(1)
SKEW1
t
t
ENS
ENS
t
DS
Figure 9. Empty Flag Timing
Figure 8. Full Flag Timing
or t
CLK
+ t
SKEW1
t
WFF
11
t
DH
t
t
ENH
ENH
t
REF
t
A
DATA READ
TM
t
ENS
t
ENS
t
ENS
NO WRITE
t
DS
DATA WRITE 2
t
t
ENH
A
t
t
t
SKEW1
ENH
ENH
t
SKEW1
DATA READ
t
COMMERCIAL AND INDUSTRIAL
WFF
NEXT DATA READ
t
FRL
t
t
TEMPERATURE RANGES
REF
t
ENS
ENS
(1)
(1)
OCTOBER 22, 2008
(1)
NO WRITE
4093 drw 11
4093 drw 10